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LT1976EFE Datasheet(PDF) 6 Page - Linear Technology |
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LT1976EFE Datasheet(HTML) 6 Page - Linear Technology |
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6 / 24 page  LT1976 6 1976f PI FU CTIO S NC (Pins 1, 3, 5): No Connection. SW (Pin 2): The SW pin is the emitter of the on-chip power NPN switch. This pin is driven up to the input pin voltage during switch on time. Inductor current drives the SW pin negative during switch off time. Negative voltage is clamped with the external catch diode. Maximum negative switch voltage allowed is –0.8V. VIN (Pin 4): This is the collector of the on-chip power NPN switch. VIN powers the internal control circuitry when a voltage on the BIAS pin is not present. High di/dt edges occur on this pin during switch turn on and off. Keep the path short from the VIN pin through the input bypass capacitor, through the catch diode back to SW. All trace inductance on this path will create a voltage spike at switch off, adding to the VCE voltage across the internal NPN. BOOST (Pin 6): The BOOST pin is used to provide a drive voltage, higher than the input voltage, to the internal bipolar NPN power switch. Without this added voltage, the typical switch voltage loss would be about 1.5V. The additional BOOST voltage allows the switch to saturate and its voltage loss approximates that of a 0.2 Ω FET structure, but with much smaller die area. CT (Pin 7): A capacitor on the CT pin determines the amount of delay time between the PGFB pin exceeding its thresh- old (VPGFB) and the PG pin set to a high impedance state. When the PGFB pin rises above VPGFB, current is sourced from the CT pin into the external capacitor. When the volt- age on the external capacitor reaches an internal clamp (VCT), the PG pin becomes a high impedance node. The resultant PG delay time is given by t = CCT • VCT/ICT. If the voltage on the PGFB pin drops below VPGFB, CCT will be discharged rapidly to 0V and PG will be active low with a 200 µAsinkcapability.IftheCTpinisclamped(PowerGood condition) during normal operation and SHDN is taken low, the CT pin will be discharged and a delay period will occur when SHDN is returned high. See the Power Good section in Applications Information for details. GND (Pins 8, 17): The GND pin connection acts as the reference for the regulated output, so load regulation will suffer if the “ground” end of the load is not at the same voltage as the GND pin of the IC. This condition will occur when load current or other currents flow through metal paths between the GND pin and the load ground. Keep the path between the GND pin and the load ground short and use a ground plane when possible. The GND pin also acts as a heat sink and should be soldered (along with the exposed leadframe) to the copper ground plane to reduce thermal resistance (see Applications Information). No Load 1A Step Response Step Response VOUT 100mV/DIV IOUT 500mA/DIV VIN = 12V TIME (1ms/DIV) 1976 G17 VOUT = 3.3V COUT = 47µF VOUT 100mV/DIV IOUT 500mA/DIV VIN = 12V TIME (1ms/DIV) 1976 G18 VOUT = 3.3V COUT = 47µF IDC = 250mA 0A 1A 0A 1A TYPICAL PERFOR A CE CHARACTERISTICS |
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