1

LTC1403/LTC1403A

1403af

APPLICATIO S

FEATURES

DESCRIPTIO

BLOCK DIAGRA

Serial 12-Bit/14-Bit, 2.8Msps

Sampling ADCs with Shutdown

s

2.8Msps Conversion Rate

s

Low Power Dissipation: 14mW

s

3V Single Supply Operation

s

2.5V Internal Bandgap Reference can be Overdriven

s

3-Wire Serial Interface

s

Sleep (10

µW) Shutdown Mode

s

Nap (3mW) Shutdown Mode

s

80dB Common Mode Rejection

s

0V to 2.5V Unipolar Input Range

s

Tiny 10-Lead MS Package

, LTC and LT are registered trademarks of Linear Technology Corporation.

s

Communications

s

Data Acquisition Systems

s

Uninterrupted Power Supplies

s

Multiphase Motor Control

s

Multiplexed Data Acquisition

2nd, 3rd and SFDR

vs Input Frequency

The LTC

rial ADCs with differential inputs. The devices draw only

4.7mA from a single 3V supply and come in a tiny 10-lead

MS package. A Sleep shutdown feature lowers power

consumption to 10

µW. The combination of speed, low

power and tiny package makes the LTC1403/LTC1403A

suitable for high speed, portable applications.

The 80dB common mode rejection allows users to elimi-

nate ground loops and common mode noise by measuring

signals differentially from the source.

The devices convert 0V to 2.5V unipolar inputs differen-

extends from ground to the supply voltage.

The serial interface sends out the conversion results

during the 16 clock cycles following CONV

↑ for compat-

ibility with standard serial interfaces. If two additional

clock cycles for acquisition time are allowed after the data

stream in between conversions, the full sampling rate of

2.8Msps can be achieved with a 50.4MHz clock.

–

+

1

2

7

3

4

S & H

GND

EXPOSED PAD

LTC1403A

10

µF

–

+

14-BIT ADC

3V

10

µF

14

8

10

9

THREE-

STATE

SERIAL

OUTPUT

PORT

2.5V

REFERENCE

TIMING

LOGIC

SDO

CONV

SCK

1403A TA01

5

6

11

FREQUENCY (MHz)

0.1

–80

–74

–68

–62

–56

1

10

100

1403A TA02

–86

–92

–98

–104

–50

–44

THD

3rd

2nd, SFDR