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LTC3733 Datasheet(PDF) 11 Page - Linear Technology |
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LTC3733 Datasheet(HTML) 11 Page - Linear Technology |
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11 / 32 page  11 LTC3733/LTC3733-1 3733f OPERATIO (Refer to Functional Diagram) Main Control Loop The IC uses a constant frequency, current mode step- down architecture. During normal operation, each top MOSFET is turned on each cycle when the oscillator sets the RS latch, and turned off when the main current comparator, I1, resets each RS latch. The peak inductor current at which I1 resets the RS latch is controlled by the voltage on the ITH pin, which is the output of the error amplifier EA. The EAIN pin receives a portion of the voltage feedback signal via the DIFFOUT pin through the internal VID DAC and is compared to the internal reference voltage. When the load current increases, it causes a slight de- crease in the EAIN pin voltage relative to the 0.6V refer- ence, which in turn causes the ITH voltage to increase until each inductor’s average current matches one third of the new load current (assuming all three current sensing resistors are equal). In Burst Mode operation and stage shedding mode, after each top MOSFET has turned off, the bottom MOSFET is turned on until either the inductor current starts to reverse, as indicated by current compara- tor I2, or the beginning of the next cycle. The top MOSFET drivers are biased from floating boot- strap capacitor CB, which is normally recharged during each off cycle through an external Schottky diode. When VIN decreases to a voltage close to VOUT, however, the loop may enter dropout and attempt to turn on the top MOSFET continuously. The dropout detector counts the number of oscillator cycles that the bottom MOSFET remains off and periodically forces a brief on period to allow CB to recharge. The main control loop is shut down by pulling the RUN pin low. Releasing RUN allows an internal 1.5 µA current source to charge soft-start capacitor CSS at the SS pin. The internal ITH voltage is then clamped to the SS voltage when CSS is slowly charged up. This “soft-start” clamping prevents abrupt current from being drawn from the input power source. When the RUN pin is low, all functions are kept in a controlled state. Low Current Operation The FCB pin is a multifunction pin: 1) an analog compara- tor input to provide regulation for a secondary winding by forcing temporary forced PWM operation and 2) a logic input to select between three modes of operation. When the FCB pin voltage is below 0.6V, the controller performs as a continuous, PWM current mode synchro- nous switching regulator. The top and bottom MOSFETs are alternately turned on to maintain the output voltage independent of direction of inductor current. When the FCB pin is below VCC – 1V but greater than 0.6V, the controller performs as a Burst Mode switching regulator. Burst Mode operation sets a minimum output current level before turning off the top switch and turns off the synchro- nous MOSFET(s) when the inductor current goes nega- tive. This combination of requirements will, at low current, force the ITH pin below a voltage threshold that will temporarily shut off both output MOSFETs until the output voltage drops slightly. There is a burst comparator having 60mV of hysteresis tied to the ITH pin. This hysteresis results in output signals to the MOSFETs that turn them on for several cycles, followed by a variable “sleep” interval depending upon the load current. The resultant output voltage ripple is held to a very small value by having the hysteretic comparator after the error amplifier gain block. When the FCB pin is tied to the VCC pin, Burst Mode operation is disabled and the forced minimum inductor current requirement is removed. This provides constant frequency, discontinuous current operation over the wid- est possible output current range. At approximately 10% of maximum designed load current, the second and third output stages are shut off and the first controller alone is active in discontinuous current mode. This “stage shed- ding” optimizes efficiency by eliminating the gate charging losses and switching losses of the other two output stages. Additional cycles will be skipped when the output load current drops below 1% of maximum designed load current in order to maintain the output voltage. This constant frequency operation is not as efficient as Burst Mode operation at very light loads, but does provide lower noise, constant frequency operating mode down to very light load conditions. Tying the FCB pin to ground will force continuous current operation. This is the least efficient operating mode, but may be desirable in certain applications. The output can |
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