72T36115L5BBI datasheet(11/56 Pages) IDT

Part #	72T36115L5BBI

Description	2.5 VOLT HIGH-SPEED TeraSyncTM FIFO 36-BIT CONFIGURATIONS

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Manufacturer	IDT [Integrated Device Technology]

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11

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

IDT72T36105/115/125 2.5V TeraSync

™

™ 36-BIT FIFO

64K x 36, 128K x 36 and 256K x 36

AC ELECTRICAL CHARACTERISTICS(1)— SYNCHRONOUS TIMING

(Commercial: VCC = 2.5V

± 5%, TA = 0°C to +70°C;Industrial: VCC = 2.5V ± 5%, TA = -40°C to +85°C)

NOTES:

1. All AC timings apply to both Standard IDT mode and First Word Fall Through mode.

2. Pulse widths less than minimum values are not allowed.

3. Values guaranteed by design, not currently tested.

4. Industrial temperature range product for the 5ns speed grade is available as a standard device. All other speed grades are available by special order.

Commercial

Com’l & Ind’l

Commercial

IDT72T36105L4-4

IDT72T36105L5

IDT72T36105L6-7 IDT72T36105L10

IDT72T36115L4-4

IDT72T36115L5

IDT72T36115L6-7 IDT72T36115L10

IDT72T36125L4-4

IDT72T36125L5

IDT72T36125L6-7 IDT72T36125L10

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Unit

fC

Clock Cycle Frequency (Synchronous)

—

225

—

200

—

150

100

MHz

tA

DataAccessTime

0.6

3.4

0.6

3.6

0.6

3.8

0.6

4.5

ns

tCLK

Clock Cycle Time

4.44

—

5

—

6.7

—

10

—

ns

tCLKH

Clock High Time

2.0

—

2.3

—

2.8

—

4.5

—

ns

tCLKL

Clock Low Time

2.0

—

2.3

—

2.8

—

4.5

—

ns

tDS

DataSetupTime

1.2

—

1.5

—

2.0

—

3.0

—

ns

tDH

DataHoldTime

0.5

—

0.5

—

0.5

—

0.5

—

ns

tENS

EnableSetupTime

1.2

—

1.5

—

2.0

—

3.0

—

ns

tENH

EnableHoldTime

0.5

—

0.5

—

0.5

—

0.5

—

ns

tLDS

LoadSetupTime

1.2

—

1.5

—

2.0

—

3.0

—

ns

tLDH

LoadHoldTime

0.5

—

0.5

—

0.5

—

0.5

—

ns

tWCSS

WCS setup time

1.2

—

1.5

—

2.0

—

3.0

—

ns

tWCSH

WCS hold time

0.5

—

0.5

—

0.5

—

0.5

—

ns

fS

Clock Cycle Frequency (SCLK)

—

10

—

10

—

10

—

10

MHz

tSCLK

Serial Clock Cycle

100

—

100

—

100

—

100

—

ns

tSCKH

Serial Clock High

45

—

45

—

45

—

45

—

ns

tSCKL

Serial Clock Low

45

—

45

—

45

—

45

—

ns

tSDS

Serial Data In Setup

15

—

15

—

15

—

15

—

ns

tSDH

Serial Data In Hold

5

—

5

—

5

—

5

—

ns

tSENS

SerialEnableSetup

5

—

5

—

5

—

5

—

ns

tSENH

Serial Enable Hold

5

—

5

—

5

—

5

—

ns

tRS

ResetPulseWidth(2)

30

—

30

—

30

—

30

—

ns

tRSS

ResetSetupTime

15

—

15

—

15

—

15

—

ns

tHRSS

HSTLResetSetupTime

4

—

4

—

4

—

4

—

μs

tRSR

Reset Recovery Time

10

—

10

—

10

—

10

—

ns

tRSF

ResettoFlagandOutputTime

—

10

—

12

—

15

—

15

ns

tWFF

Write Clock to FF or IR

—

3.4

—

3.6

—

3.8

—

4.5

ns

tREF

Read Clock to EF or OR

—

3.4

—

3.6

—

3.8

—

4.5

ns

tPAFS

WriteClocktoSynchronousProgrammableAlmost-FullFlag

—

3.4

—

3.6

—

3.8

—

4.5

ns

tPAES

Read Clock to Synchronous Programmable Almost-Empty Flag

—

3.4

—

3.6

—

3.8

—

4.5

ns

tERCLK

RCLK to Echo RCLK output

—

3.8

—

4

—

4.3

—

5

ns

tCLKEN

RCLK to Echo REN output

—

3.4

—

3.6

—

3.8

—

4.5

ns

tRCSLZ

RCLK to Active from High-Z(3)

—

3.4

—

3.6

—

3.8

—

4.5

ns

tRCSHZ

RCLK to High-Z(3)

—

3.4

—

3.6

—

3.8

—

4.5

ns

tSKEW1

Skew time between RCLK and WCLK for EF/OR and FF/IR

3.5

—

4

—5

—7

—

ns

tSKEW2

Skew time between RCLK and WCLK for PAE and PAF

4—

5—

6

—

8—

ns

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