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72T18125L4-4BBG Datasheet(PDF) 7 Page - Integrated Device Technology

Part # 72T18125L4-4BBG
Description  2.5 VOLT HIGH-SPEED TeraSync??FIFO
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

72T18125L4-4BBG Datasheet(HTML) 7 Page - Integrated Device Technology

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COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
PIN DESCRIPTION
Symbol
Name
I/O TYPE
Description
ASYR(1) Asynchronous
LVTTL
AHIGHonthisinputduringMasterResetwillselectSynchronousreadoperationfortheoutputport.ALOW
Read Port
INPUT
willselectAsynchronousoperation.IfAsynchronousisselectedtheFIFOmustoperateinIDTStandardmode.
ASYW(1) Asynchronous
LVTTL
A HIGH on this input during Master Reset will select Synchronous write operation for the input port. A LOW
WritePort
INPUT
willselectAsynchronousoperation.
BE(1)
Big-Endian/
LVTTL
During Master Reset, a LOW on BE will select Big-Endian operation. A HIGH on BE during Master Reset
Little-Endian
INPUT
willselectLittle-Endianformat.
D0–D17 DataInputs
HSTL-LVTTL Data inputs for an 18- or 9-bit bus. When in 18- or 9-bit mode, the unused input pins should be tied to GND.
INPUT
EF/OR
EmptyFlag/
HSTL-LVTTL IntheIDTStandardmode,theEFfunctionisselected.EFindicateswhetherornottheFIFOmemoryisempty.
OutputReady
OUTPUT
In FWFT mode, the OR function is selected. OR indicates whether or not there is valid data available at the
outputs.
ERCLK RCLK Echo
HSTL-LVTTL Read clock Echo output, only available when the Read is setup for Synchronous mode.
OUTPUT
EREN
Read Enable Echo HSTL-LVTTL Read Enable Echo output, only available when the Read is setup for Synchronous mode.
OUTPUT
FF/IR
Full Flag/
HSTL-LVTTL In the IDT Standard mode, the FF function is selected. FF indicates whether or not the FIFO memory is
Input Ready
OUTPUT
full. In the FWFT mode, the IR function is selected. IR indicates whether or not there is space available for
writing to the FIFO memory.
FSEL0(1) FlagSelectBit0
LVTTL
During Master Reset, this input along with FSEL1 and the LD pin, will select the default offset values for the
INPUT
programmable flags PAE and PAF. There are up to eight possible settings available.
FSEL1(1) FlagSelectBit1
LVTTL
During Master Reset, this input along with FSEL0 and the LD pin will select the default offset values for the
INPUT
programmable flags PAE and PAF. There are up to eight possible settings available.
FWFT/ FirstWordFall
HSTL-LVTTL During Master Reset, selects First Word Fall Through or IDT Standard mode. After Master Reset, this pin
SI
Through/Serial In
INPUT
functions as a serial input for loading offset registers. If Asynchronous operation of the read port has been
selected then the FIFO must be setup in IDT Standard mode.
HF
Half-FullFlag
HSTL-LVTTL HF indicates whether the FIFO memory is more or less than half-full.
OUTPUT
IP(1)
InterspersedParity
LVTTL
DuringMasterReset,aLOWonIPwillselectNon-InterspersedParitymode.AHIGHwillselectInterspersed
INPUT
Paritymode.
IW(1)
InputWidth
LVTTL
This pin, along with OW, selects the bus width of the write port. See Table 1 for bus size configuration.
INPUT
LD
Load
HSTL-LVTTL This is a dual purpose pin. During Master Reset, the state of the LD input along with FSEL0 and FSEL1,
INPUT
determinesoneofeightdefaultoffsetvaluesforthePAEandPAFflags,alongwiththemethodbywhichthese
offsetregisterscanbeprogrammed,parallelorserial(seeTable2).AfterMasterReset,thispinenableswriting
to and reading from the offset registers. THIS PIN MUST BE HIGH AFTER MASTER RESET TO WRITE
OR READ DATA TO/FROM THE FIFO MEMORY.
MARK
MarkforRetransmit HSTL-LVTTL Whenthispinisassertedthecurrentlocationofthereadpointerwillbemarked.AnysubsequentRetransmit
INPUT
operationwillresetthereadpointertothisposition.
MRS
MasterReset
HSTL-LVTTL MRS initializes the read and write pointers to zero and sets the output register to all zeroes. During Master
INPUT
Reset, the FIFO is configured for either FWFT or IDT Standard mode, Bus-Matching configurations,
Synchronous/Asynchronousoperationofthereadorwriteport,oneofeightprogrammableflagdefaultsettings,
serialorparallelprogrammingoftheoffsetsettings,Big-Endian/Little-Endianformat,zerolatencytimingmode,
interspersedparity,andsynchronousversusasynchronousprogrammableflagtimingmodes.
OE
OutputEnable
HSTL-LVTTL OE provides Asynchronous three-state control of the data outputs, Qn.During a Master or Partial Reset the
INPUT
OE input is the only input that provide High-Impedance control of the data outputs.
OW(1)
OutputWidth
LVTTL
This pin, along with IW, selects the bus width of the read port. See Table 1 for bus size configuration.
INPUT
PAE
Programmable
HSTL-LVTTL PAE goes LOW if the number of words in the FIFO memory is less than offset n, which is stored in the Empty
Almost-EmptyFlag
OUTPUT
Offsetregister.PAEgoesHIGHifthenumberofwordsintheFIFOmemoryisgreaterthanorequaltooffsetn.
PAF
Programmable
HSTL-LVTTL PAF goes HIGH if the number of free locations in the FIFO memory is more than offset m, which is stored in
Almost-FullFlag
OUTPUT
theFullOffsetregister.PAFgoesLOWifthenumberoffreelocationsintheFIFOmemoryislessthanorequal
tom.
PFM(1)
Programmable
LVTTL
DuringMasterReset,aLOWonPFMwillselectAsynchronousProgrammableflagtimingmode.AHIGHon
Flag Mode
INPUT
PFMwillselectSynchronousProgrammableflagtimingmode.


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