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72T18125L6-7BB Datasheet(PDF) 4 Page - Integrated Device Technology |
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72T18125L6-7BB Datasheet(HTML) 4 Page - Integrated Device Technology |
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4 / 56 page  4 COMMERCIALANDINDUSTRIAL TEMPERATURERANGES IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/ 8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9 DESCRIPTION: The IDT72T1845/72T1855/72T1865/72T1875/72T1885/72T1895/ 72T18105/72T18115/72T18125 are exceptionally deep, extremely high speed,CMOSFirst-In-First-Out(FIFO)memorieswithclockedreadandwrite controls and a flexible Bus-Matching x18/x9 data flow. These FIFOs offer several key user benefits: • Flexible x18/x9 Bus-Matching on both read and write ports • AuserselectableMARKlocationforretransmit • User selectable I/O structure for HSTL or LVTTL • Asynchronous/Synchronous translation on the read or write ports • Thefirstworddatalatencyperiod,fromthetimethefirstwordiswrittentoan empty FIFO to the time it can be read, is fixed and short. • High density offerings up to 9 Mbit Bus-Matching TeraSync FIFOs are particularly appropriate for network, video,telecommunications,datacommunicationsandotherapplicationsthat needtobufferlargeamountsofdataandmatchbussesofunequalsizes. Each FIFO has a data input port (Dn) and a data output port (Qn), both of whichcanassumeeithera18-bitora9-bitwidthasdeterminedbythestateof external control pins Input Width (IW) and Output Width (OW) pin during the MasterResetcycle. TheinputportcanbeselectedaseitheraSynchronous(clocked)interface, or Asynchronous interface. During Synchronous operation the input port is controlledbyaWriteClock(WCLK)inputandaWriteEnable(WEN)input. Data present on the Dn data inputs is written into the FIFO on every rising edge of WCLK when WEN is asserted. During Asynchronous operation only the WR inputisusedtowritedataintotheFIFO.DataiswrittenonarisingedgeofWR, theWEN inputshouldbetiedtoitsactivestate,(LOW). TheoutputportcanbeselectedaseitheraSynchronous(clocked)interface, or Asynchronous interface. During Synchronous operation the output port is controlledbyaReadClock(RCLK)inputandReadEnable(REN)input. Data is read from the FIFO on every rising edge of RCLK when REN is asserted. DuringAsynchronousoperationonlytheRDinputisusedtoreaddatafromthe FIFO. Data is read on a rising edge of RD, the REN input should be tied to its activestate,LOW.WhenAsynchronousoperationisselectedontheoutputport theFIFOmustbeconfiguredforStandardIDTmode,alsotheRCSshouldbe tiedLOWandtheOEinputusedtoprovidethree-statecontroloftheoutputs,Qn. Theoutputportcanbeselectedforeither2.5VLVTTLorHSTLoperation, thisoperationisselectedbythestateoftheRHSTLinputduringamasterreset. AnOutputEnable(OE)inputisprovidedforthree-statecontroloftheoutputs. AReadChipSelect(RCS)inputisalsoprovided,theRCSinputissynchronized tothereadclock,andalsoprovidesthree-statecontroloftheQndataoutputs. When RCS is disabled, the data outputs will be high impedance. During Asynchronousoperationoftheoutputport,RCSshouldbeenabled,heldLOW. Echo Read Enable, EREN and Echo Read Clock, ERCLK outputs are provided. These are outputs from the read port of the FIFO that are required forhighspeeddatacommunication,toprovidetightersynchronizationbetween thedatabeingtransmittedfromtheQnoutputsandthedatabeingreceivedby theinputdevice.Datareadfromthereadportisavailableontheoutputbuswith respect to EREN and ERCLK, this is very useful when data is being read at highspeed.TheERCLKandERENoutputsarenon-functionalwhentheRead port is setup for Asynchronous mode. ThefrequenciesofboththeRCLKandtheWCLKsignalsmayvaryfrom0 tofMAXwithcompleteindependence. Therearenorestrictionsonthefrequency of the one clock input with respect to the other. Therearetwopossibletimingmodesofoperationwiththesedevices:IDT Standard mode and First Word Fall Through (FWFT) mode. InIDTStandardmode,thefirstwordwrittentoanemptyFIFOwillnotappear onthedataoutputlinesunlessaspecificreadoperationisperformed.Aread operation,whichconsistsofactivatingRENandenablingarisingRCLKedge, willshiftthewordfrominternalmemorytothedataoutputlines. In FWFT mode, the first word written to an empty FIFO is clocked directly tothedataoutputlinesafterthreetransitionsoftheRCLKsignal.ARENdoes not have to be asserted for accessing the first word. However, subsequent words written to the FIFO do require a LOW on REN for access. The state of theFWFT/SIinputduringMasterResetdeterminesthetimingmodeinuse. For applications requiring more data storage capacity than a single FIFO canprovide,theFWFTtimingmodepermitsdepthexpansionbychainingFIFOs inseries(i.e.thedataoutputsofoneFIFOareconnectedtothecorresponding data inputs of the next). No external logic is required. These FIFOs have five flag pins, EF/OR (Empty Flag or Output Ready), FF/IR (Full Flag or Input Ready), HF (Half-full Flag), PAE (Programmable Almost-Emptyflag)andPAF(ProgrammableAlmost-Fullflag). TheEFandFF functions are selected in IDT Standard mode. The IR and OR functions are selected in FWFT mode. HF, PAE and PAF are always available for use, irrespectiveoftimingmode. PAE and PAFcanbeprogrammedindependentlytoswitchatanypointin memory. Programmableoffsetsdeterminetheflagswitchingthresholdandcan beloadedbytwomethods:parallelorserial. Eightdefaultoffsetsettingsarealso provided,sothatPAEcanbesettoswitchatapredefinednumberoflocations from the empty boundary and the PAF threshold can also be set at similar predefinedvaluesfromthefullboundary. Thedefaultoffsetvaluesaresetduring Master Reset by the state of the FSEL0, FSEL1, and LD pins. For serial programming, SEN together with LD on each rising edge of SCLK,areusedtoloadtheoffsetregistersviatheSerialInput(SI). Forparallel programming,WENtogetherwithLDoneachrisingedgeofWCLK,areused to load the offset registers via Dn. REN together with LD on each rising edge ofRCLKcanbeusedtoreadtheoffsetsinparallelfromQnregardlessofwhether serialorparalleloffsetloadinghasbeenselected. DuringMasterReset(MRS)thefollowingeventsoccur: thereadandwrite pointers are set to the first location of the FIFO. The FWFT pin selects IDT Standard mode or FWFT mode. The Partial Reset (PRS) also sets the read and write pointers to the first location of the memory. However, the timing mode, programmable flag programmingmethod,anddefaultorprogrammedoffsetsettingsexistingbefore PartialResetremainunchanged.Theflagsareupdatedaccordingtothetiming modeandoffsetsineffect. PRSisusefulforresettingadeviceinmid-operation, whenreprogrammingprogrammableflagswouldbeundesirable. ItisalsopossibletoselectthetimingmodeofthePAE(ProgrammableAlmost- Empty flag) and PAF (Programmable Almost-Full flag) outputs. The timing modescanbesettobeeitherasynchronousorsynchronousforthe PAEand PAFflags. IfasynchronousPAE/PAFconfigurationisselected, the PAE isasserted LOWontheLOW-to-HIGHtransitionofRCLK.PAEisresettoHIGHontheLOW- to-HIGHtransitionofWCLK.Similarly,thePAFisassertedLOWontheLOW- to-HIGH transition of WCLK and PAF is reset to HIGH on the LOW-to-HIGH transitionofRCLK. IfsynchronousPAE/PAFconfigurationisselected,thePAEisassertedand updated on the rising edge of RCLK only and not WCLK. Similarly, PAF is assertedandupdatedontherisingedgeofWCLKonlyandnotRCLK.Themode desiredisconfiguredduringMasterResetbythestateoftheProgrammableFlag Mode (PFM) pin. ThisdeviceincludesaRetransmitfromMarkfeaturethatutilizestwocontrol inputs,MARKand,RT(Retransmit).IftheMARKinputisenabledwithrespect totheRCLK,thememorylocationbeingreadatthatpointwillbemarked.Any subsequentretransmitoperation,RTgoesLOW,willresetthereadpointerto this‘marked’location. |
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