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NTQS6463R2 Datasheet(PDF) 5 Page - ON Semiconductor

Part # NTQS6463R2
Description  Power MOSFET
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Manufacturer  ONSEMI [ON Semiconductor]
Direct Link  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

NTQS6463R2 Datasheet(HTML) 5 Page - ON Semiconductor

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NTQS6463
http://onsemi.com
5
Figure 8. Gate−to−Source and
Drain−to−Source Voltage versus Total Charge
Figure 9. Resistive Switching Time Variation
versus Gate Resistance
Qg, TOTAL GATE CHARGE (nC)
RG, GATE RESISTANCE (W)
24
20
16
12
8
4
0
0
1
2
3
4
5
10
1
10
100
Figure 10. Diode Forward Voltage versus
Current
−VSD, SOURCE−TO−DRAIN VOLTAGE (V)
0.7
0.6
0.5
0.4
0
0.4
0.8
28
100
1000
1.2
VDD = −16 V
ID = −6.8 A
VGS = −4.5 V
VGS = 0 V
TJ = 25°C
TJ = 25°C
ID = −6.8 A
VGS = −4.5
QT
Q1
Q2
td(off)
td(on)
tf
tr
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
0.1
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
1
10
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
0.01
VGS = −4.5 V
SINGLE PULSE
TC = 25°C
10
0.1
dc
10 ms
1
100
100
Mounted on 2
″ sq. FR4 board (1″ sq. 1 oz. Cu 0.06″ thick single sided)
100
ms
10
ms
1 ms
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain−to−source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
junction temperature and a case temperature (TC) of 25°C.
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance −
General Data and Its Use.”
Switching between the off−state and the on−state may
traverse any load line provided neither rated peak current
(IDM) nor rated voltage (VDSS) is exceeded and the
transition time (tr, tf) do not exceed 10
ms. In addition the
total power averaged over a complete switching cycle must
not exceed (TJ(MAX) − TC)/(RθJC).
A Power MOSFET designated E−FET can be safely used
in switching circuits with unclamped inductive loads. For
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is
to rate in terms of energy, avalanche energy capability is not
a constant. The energy rating decreases non−linearly with an
increase of peak current in avalanche and peak junction
temperature.
Although many E−FETs can withstand the stress of
drain−to−source avalanche at currents up to rated pulsed
current (IDM), the energy rating is specified at rated
continuous current (ID), in accordance with industry
custom. The energy rating must be derated for temperature.
Maximum energy at currents below rated continuous ID can
safely be assumed to equal the values indicated.


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