ACE25QA160G

16M BIT SPI NOR FLASH

VER 1.1

11

Read Status Register (05H)

See Figure 3 the Read Status Register (RDSR) instruction is for reading the Status Register. The Status

Register may be read at any time, even while a Program, Erase or Write Status Register cycle is in

progress. When one of these cycles is in progress, it is recommended to check the Write in Progress (WIP)

bit before sending a new instruction to the device. It is also possible to read the Status Register

continuously.

For instruction code “05H”, the SO will output Status Register bits S7~S0.

Write Status Register (01H)

See Figure 4, the Write Status Register instruction allows new values to be written to the Status Register.

Before it can be accepted, a Write Enable instruction must previously have been executed. After the Write

Enable instruction has been decoded and executed, the device sets the Write Enable Latch (WEL).

The Write Status Register instruction has no effect on S6, S5, S1 and S0 of the Status Register. S6 and S5

are always read as 0. /CS must be driven high after the eighth or sixteen bit of the data byte has been

latched in. If not, the Write Status Register instruction is not executed. As soon as Chip Select (CS#) is

driven High, the self-timed Write Status Register cycle (the duration is tW) is initiated. While the Write

Status Register cycle is in progress, reading Status Register to check the Write In Progress (WIP) bit is

achievable. The Write In Progress (WIP) bit is 1 during the self-timed Write Status Register cycle, and turn

to 0 on the completion of the Write Status Register. When the cycle is completed, the Write Enable Latch

(WEL) is reset to 0. The Write Status Register (WRSR) instruction allows the user to change the values of

the Block Protect (BP2, BP1, BP0) bits, which are utilized to define the size of the read-only area. The Write

Status Register (WRSR) instruction also allows the user to set or reset the Status Register Protect (SRP)

bit in accordance with the Write Protect (WP#) signal, by setting which the device can enter into Hardware

Protected Mode (HPM). The Write Status Register (WRSR) instruction is not executed once enter into the

Hardware Protected Mode (HPM).

Figure 3. Read Status Register Sequence Diagram

Figure 4. Write Status Register Sequence Diagram