ALD810017/ALD910017

Advanced Linear Devices, Inc.

2 of 6

SCHEMATIC DIAGRAM OF A TYPICAL

CONNECTION FOR A TWO-SUPERCAP STACK

1-8 DENOTES PACKAGE PIN NUMBERS

C1-C2 DENOTES SUPERCAPACITORS

M1

M2

2

3, 8

4

1, 5

6

7

ALD9100XX

C1

C2

+

+

V+ ≤ +15.0V

V1

IDS(ON) ≤ 80mA

SCHEMATIC DIAGRAM OF A TYPICAL

CONNECTION FOR A FOUR-SUPERCAP STACK

1-16 DENOTES PACKAGE PIN NUMBERS

C1-C4 DENOTES SUPERCAPACITORS

V+ ≤ +15.0V

1, 5, 8, 16

2, 12

3

4

6

7

9

10

11

13

14

15

ALD8100XX

C4

+

+

C3

+

C2

+

C1

M1

M2

M3

M4

V1

V2

V3

IDS(ON) ≤ 80mA

GENERAL DESCRIPTION (CONT.)

The voltage dependent characteristic of the ALD810017/

ALD910017 on-resistance is effective in controlling excessive volt-

age rise across a supercapacitor when connected across it. In se-

ries-connected supercapacitor stacks, when one supercapacitor

voltage rises, the voltage of the other supercapacitors drops, with

the ones that have the highest leakage currents having the lowest

supercapacitor voltages. The SAB MOSFETs connected across

these supercapacitors would exhibit complementary opposing cur-

rent levels, resulting in little additional leakage currents other than

those caused by the supercapacitors themselves.

For technical assistance, please contact ALD technical support at

techsupport@aldinc.com.

APPLYING THE ALD810017/ALD910017:

1) Select a maximum supercapacitor leakage current limit for any

supercapacitor used in the stack. This is the same as output cur-

supercapacitor leakage current meets this maximum current limit

before use in the stack.

same voltage as the maximum desired operating voltage of the

3) Determine that the operating voltage margin, due to various

tolerances and/or temperature effects, is adequate for the intended

operating environment of the supercapacitor.