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TPS22970YZPR Datasheet(PDF) 10 Page - Texas Instruments |
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TPS22970YZPR Datasheet(HTML) 10 Page - Texas Instruments |
10 / 22 page SMPS ON OFF TPS22970 V IN V OUT R L C L GND ON GND C IN Copyright © 2017, Texas Instruments Incorporated J(max) A D(max) JA T T P - = θ 10 TPS22970 SLVSDF2 – MAY 2017 www.ti.com Product Folder Links: TPS22970 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information 9.1.1 Input Capacitor (CIN) It is recommended to use a capacitor between VIN and GND close to the device pins. This helps limit the voltage droop on the input supply caused by transient inrush currents when the switch is turned on into a discharged capacitor at the load. A 1-μF ceramic capacitor, CIN, is usually sufficient. Higher values of CIN can be used to further reduce the voltage droop. 9.1.2 Output Capacitor (CL) A CIN greater than CL is highly recommended due to the integrated body diode in the NMOS switch. A CL greater than CIN can cause VOUT to exceed VIN when the system supply is removed. This could result in current flow through the body diode from VOUT to VIN. 9.1.3 Thermal Consideration It is recommended to limit the junction temperature (TJ) to below 125°C. To calculate the maximum allowable dissipation, PD(max) for a given output current and ambient temperature, use Equation 1 as a guideline: where • PD(max) is maximum allowable power dissipation • TJ(max) is maximum allowable junction temperature • TA is ambient temperature of the device • ΘJA is junction to air thermal impedance. See the Thermal Information section. This parameter is highly dependent upon board layout (1) 9.2 Typical Application Figure 3. Typical Application Circuit |
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