SN65LV1023/SN65LV1224

30MHz TO 66MHz, 10:1 LVDS SERIALIZER/DESERIALIZER

SLLS527G − FEBRUARY 2002 − REVISED JANUARY 2005

9

POST OFFICE BOX 655303

serializer timing requirements for TCLK over recommended operating supply and temperature

ranges (unless otherwise specified)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

tTCP

Transmit clock period

15.15

T

33.33

ns

tTCIH

Transmit clock high time

0.4T

0.5T

0.6T

ns

tTCIL

Transmit clock low time

0.4T

0.5T

0.6T

ns

tt(CLK)

TCLK input transition time

3

6

ns

tJIT

TCLK input jitter

See Figure 17

150

ps

(RMS)

serializer switching characteristics over recommended operating supply and temperature ranges

(unless otherwise specified)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

tTLH(L)

LVDS low-to-high transition time

RL = 27 Ω, CL = 10 pF to GND,

0.2

0.4

ns

tLTHL(L) LVDS high-to-low transition time

RL = 27 Ω, CL = 10 pF to GND,

See Figure 4

0.25

0.4

ns

tsu(DI)

DIN0−DIN9 setup to TCLK

RL = 27 Ω, CL = 10 pF to GND,

0.5

ns

tsu(DI)

DIN0−DIN9 hold from TCLK

RL = 27 Ω, CL = 10 pF to GND,

See Figure 7

4

ns

td(HZ)

DO

± high-to-high-impedance-state delay

2.5

5

td(LZ)

DO

± low-to-high-impedance-state delay

2.5

5

td(ZH)

DO

± high-to-high-impedance-state-to-

high delay

RL = 27 Ω, CL = 10 pF to GND,

See Figure 8

5

10

ns

td(ZL)

DO

± high-to-high-impedance-state-to-low

delay

See Figure 8

6.5

10

tw(SPW) SYNC pulse duration

RL = 27 Ω, See Figure 10

6

×tTCP

ns

t(PLD)

Serializer PLL lock time

RL = 27 Ω, See Figure 10

1026

×tTCP

ns

td(S)

Serializer delay

RL = 27 Ω, See Figure 11

t

TCP

2

) 3.6

ns

tDJIT

Deterministic jitter

30 MHz

RL = 27 Ω, CL = 10 pF to GND

230

ps

tDJIT

Deterministic jitter

66 MHz

RL = 27 Ω, CL = 10 pF to GND

150

ps

tRJIT

Random jitter

RL = 2.7 Ω, CL = 10 pF to GND

10

19

ps

(RMS)