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HT48RA0-2 Datasheet(PDF) 9 Page - Holtek Semiconductor Inc |
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HT48RA0-2 Datasheet(HTML) 9 Page - Holtek Semiconductor Inc |
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9 / 30 page  HT48RA0-2/HT48CA0-2 Rev. 2.20 9 September 5, 2008 Carrier The HT48RA0-2/HT48CA0-2 provides a carrier output which shares the pin with PC0. It can be selected to be a carrier output (REM) or level output pin (PC0) by code option. If the carrier output option is selected, setting PC0= ²0² to enable carrier output and setting PC0=²1² to disable it at low level output. The clock source of the carrier is implemented by in- struction clock (system clock divided by 4) and pro- cessed by a frequency divider to yield various carry frequency. Carry Frequency= Clock Source m2 n where m=2 or 3 and n=0~3, both are selected by code option. If m=2, the duty cycle of the carrier output is 1/2 duty. If m=3, the duty cycle of the carrier output can be 1/2 duty or 1/3 duty also determined by code option (with the exception of n=0). Detailed selection of the carrier duty is shown below: m ´2 n Duty Cycle 2, 4, 8, 16 1/2 31/3 6, 12, 24 1/2or1/3 The following table shows examples of carrier fre- quency selection. fSYS fCARRIER Duty m ´2 n 455kHz 37.92kHz 1/3 only 3 56.9kHz 1/2 only 2 Input/Output Ports There are an 8-bit bidirectional input/output port, a 4-bit input with 2-bit I/O port and one-bit output port in the HT48RA0-2/HT48CA0-2, labeled PA, PB and PC which are mapped to [12H], [14H], [16H] of the RAM, respec- tively. Each bit of PA can be selected as NMOS output or Schmitt trigger with pull-high resistor by software in- struction. PB0~PB1 have the same structure with PA, while PB2~PB5 can only be used for input operation (Schmitt trigger with pull-high resistors). PC is only one-bit output port shares the pin with carrier output. If the level option is selected, the PC is CMOS output. Both PA and PB for the input operation, these ports are non-latched, that is, the inputs should be ready at the T2 rising edge of the instruction ²MOV A, [m]² (m=12H or 14H). For PA, PB0~PB1 and PC output operation, all data are latched and remain unchanged until the output latch is rewritten. The chip reset status of the registers is summarized in the following table: Register Reset (Power On) WDT Time-out (Normal Operation) RES Reset (Normal Operation) RES Reset (HALT) WDT Time-out (HALT)* Program Counter 000H 000H 000H 000H 000H MP -xxx xxxx -uuu uuuu -uuu uuuu -uuu uuuu -uuu uuuu ACC xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu TBLP xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu TBLH --xx xxxx --uu uuuu --uu uuuu --uu uuuu --uu uuuu STATUS --00 xxxx --1u uuuu --uu uuuu --01 uuuu --11 uuuu PA 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu PB 0011 1111 0011 1111 0011 1111 0011 1111 uuuu uuuu PC ---- ---1 ---- ---1 ---- ---1 ---- ---1 ---- ---u Note: ²u² means unchanged ²x² means unknown ´ C l o c k S o u r c e ( S y s t e m C l o c k / 4 ) 3 - b i t C o u n t e r C o d e O p t i o n 1 / 2 1 / 3 F r e q u e n c y D i v i d e r V D D R e a d p a t h f o r r e a d - m o d i f y - w r i t e P C 0 D a t a R e g i s t e r R E M / P C 0 C o d e O p t i o n ( c a r r i e r o r l e v e l ) C a r r i e r D u t y S e l e c t 1 / 2 o r 1 / 3 d u t y L e v e l C a r r i e r C a r r i e r L e v e l Carrier/Level Output |
Similar Part No. - HT48RA0-2_08 |
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Similar Description - HT48RA0-2_08 |
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