R5F523T5AGFL datasheet(3/98 Pages) RENESAS

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R5F523T5AGFL Datasheet(PDF) 3 Page - Renesas Technology Corp

Part #	R5F523T5AGFL

Description	40-MHz 32-bit RX MCUs, built-in FPU, 65.6 DMIPS

Download	98 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

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R01DS0248EJ0110 Rev.1.10

Page 3 of 98

Jan 13, 2016

RX23T Group

1. Overview

Interrupt

Interrupt controller (ICUb)

 Interrupt vectors: 83

 External interrupts: 7 (NMI, IRQ0 to IRQ5 pins)

 Non-maskable interrupts: 5 (NMI pin, oscillation stop detection interrupt, voltage monitoring 1

interrupt, voltage monitoring 2 interrupt, and IWDT interrupt)

 16 levels specifiable for the order of priority

DMA

Data transfer controller

(DTCa)

 Transfer modes: Normal transfer, repeat transfer, and block transfer

 Activation sources: Interrupts

 Chain transfer function

I/O ports

General I/O ports

64-/52-/48-pin

 I/O: 50/40/37

 Input: 1/1/1

 Pull-up resistors: 50/40/37

 Open-drain outputs: 42/32/29

 5-V tolerance: 2/2/2

Multi-function pin controller (MPC)

Capable of selecting the input/output function from multiple pins

Timers

Multi-function timer pulse

unit 3 (MTU3c)

 6 units (16bis × 6 channels)

 Provides up to 16 pulse-input/output lines and three pulse-input lines

 Select from among fourteen counter-input clock signals for each channel (PCLK/1, PCLK/2, PCLK/4,

PCLK/8, PCLK/16, PCLK/32, PCLK/64, PCLK/256, PCLK/1024, MTCLKA, MTCLKB, MTCLKC,

MTCLKD, MTIOC1A) other than channel 1/3/4, for which only eleven signals are available, channel 2

for 12, channel 5 for 10

 26 output compare/input capture registers

 Counter clear operation (with compare match- or input capture-sourced simultaneous counter clear

capability)

 Simultaneous writing to multiple timer counters (TCNT)

 Simultaneous register input/output by synchronous counter operation

 Buffer operation

 Cascaded operation

 28 interrupt sources

 Automatic transfer of register data

 Pulse output modes: Toggle/PWM/complementary PWM/reset-synchronized PWM

 Complementary PWM output mode

3-phase non-overlapping waveform output for inverter control

Automatic dead time setting

Adjustable PWM duty cycle: from 0 to 100%

A/D conversion request delaying function

Interrupt at crest/trough can be skipped

Double buffer function

 Reset-synchronized PWM mode

Outputs three phases each for positive and negative PWM waveforms in user-specified duty cycle

 Phase counting modes: 16-bit mode (channel 1 and 2)/32-bit mode (channel 1 and 2)

 Dead time compensation counter function

 A/D converter start trigger can be generated

 A/D converter start triggers can be skipped

 Signals from the input capture and external counter clock pins are input via a digital filter

Port output enable 3

(POE3b)

Controls the high-impedance state of the MTU’s waveform output pins

Compare match timer

(CMT)

 (16 bits × 2 channels) × 2 units

 Select from among four clock signals (PCLK/8, PCLK/32, PCLK/128, PCLK/512)

Independent watchdog

timer (IWDTa)

 14 bits × 1 channel

 Count clock: Dedicated low-speed on-chip oscillator for the IWDT

Frequency divided by 1, 16, 32, 64, 128, or 256

8-bit timer (TMR)

 (8 bits × 2 channels) × 2 units

 Seven internal clocks (PCLK/1, PCLK/2, PCLK/8, PCLK/32, PCLK/64, PCLK/1024, and PCLK/8192)

and an external clock can be selected

 Pulse output and PWM output with any duty cycle are available

 Two channels can be cascaded and used as a 16-bit timer

 Generates A/D conversion start trigger

 Generates baud rate clock for the SCI5

Table 1.1

Outline of Specifications (2/3)

Classification

Module/Function

Description

Similar Part No. - R5F523T5AGFL

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Similar Description - R5F523T5AGFL

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