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R5F565N4ADLK Datasheet(PDF) 6 Page - Renesas Technology Corp

Part # R5F565N4ADLK
Description  120-MHz, 32-bit RX MCU, on-chip FPU, 240 DMIPS, up to 1-MB flash memory,
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

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RX65N Group, RX651 Group
1. Overview
R01DS0276EJ0100 Rev.1.00
Page 6 of 190
Aug 24, 2016
Timers
Realtime clock (RTCd)
 Clock sources: Main clock, sub clock
 Selection of the 32-bit binary count in time count/second unit possible
 Clock and calendar functions
 Interrupt sources: Alarm interrupt, periodic interrupt, and carry interrupt
 Battery backup operation
 Time-capture facility for three values
 Event linking by the ELC
Watchdog timer (WDTA)
 14 bits × 1 channel
 Select from among 6 counter-input clock signals (PCLKB/4, PCLKB/64, PCLKB/128,
PCLKB/512, PCLKB/2048, PCLKB/8192)
Independent watchdog
timer (IWDTa)
 14 bits × 1 channel
 Counter-input clock: IWDT-dedicated on-chip oscillator
 Dedicated clock/1, dedicated clock/16, dedicated clock/32, dedicated clock/64,
dedicated clock/128, dedicated clock/256
 Window function: The positions where the window starts and ends are specifiable (the
window defines the timing with which refreshing is enabled and disabled).
 Event linking by the ELC
Communication
function
Ethernet controller
(ETHERC)
 Input and output of Ethernet/IEEE 802.3 frames
 Transfer at 10 or 100 Mbps
 Full- and half-duplex modes
 MII (Media Independent Interface) or RMII (Reduced Media Independent Interface) as
defined in IEEE 802.3u
 Detection of Magic PacketsTM*1 or output of a “wake-on-LAN” signal (WOL)
 Compliance with flow control as defined in IEEE 802.3x standards
DMA controller for
Ethernet controller
(EDMACa)
 Alleviation of CPU load by the descriptor control method
 Transmission FIFO: 2 Kbytes; Reception FIFO: 2 Kbytes
USB 2.0 FS host/
function module (USBb)
 Includes a UDC (USB Device Controller) and transceiver for USB 2.0 FS
 One port
 Compliance with the USB 2.0 specification
 Transfer rate: Full speed (12 Mbps), low speed (1.5 Mbps) (host only)
 Both self-power mode and bus power are supported
 OTG (On the Go) operation is possible (low-speed is not supported)
 Incorporates 2 Kbytes of RAM as a transfer buffer
 External pull-up and pull-down resistors are not required
Serial communications
interfaces
(SCIg, SCIh, SCIi)
 13 channels (SCIg: 10 channels + SCIh: 1 channel + SCIi: 2 channels)
 SCIg, SCIh, SCIi
Serial communications modes: Asynchronous, clock synchronous, and smart-card
interface
Multi-processor function
On-chip baud rate generator allows selection of the desired bit rate
Choice of LSB-first or MSB-first transfer
Start-bit detection: Level or edge detection is selectable.
Simple I2C
Simple SPI
9-bit transfer mode
Bit rate modulation
Double-speed mode
 SCIg, SCIh
Average transfer rate clock can be input from TMR timers for SCI5, SCI6, and SCI12
Event linking by the ELC (only on channel 5)
 SCIh
Supports the serial communications protocol, which contains the start frame and
information frame
Supports the LIN format
 SCIi
Data can be transmitted or received in sequence by the 16-byte FIFO buffers of the
transmission and reception unit
Table 1.1
Outline of Specifications (5/8)
Classification
Module/Function
Description


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