W39V040FA

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programmed/erased whether the output data, DQ0/DQ1 at the address 7FFF2, is "0" or "1". The #TBL

will lock the whole 64Kbytes top boot block, it will not partially lock the 16Kbytes boot block. You can

check the DQ2/DQ3 at the address 7FFF2 to see whether the #TBL/#WP pin is in low or high state. If

the DQ2 is "0", it means the #TBL pin is tied to high state. In such condition, whether boot block can

be programmed/erased or not will depend on software setting. On the other hand, if the DQ2 is "1", it

means the #TBL pin is tied to low state, then boot block is locked no matter how the software is set.

Like the DQ2, the DQ3 inversely mirrors the #WP state. If the DQ3 is "0", it means the #WP pin is in

high state, then all the sectors except the boot block can be programmed/erased. On the other hand, if

the DQ3 is "1", then all the sectors except the boot block are programmed/erased inhibited.

To return to normal operation, perform a three-byte command sequence (or an alternate single-byte

command) to exit the identification mode. For the specific code, see Command Codes for

Identification/Boot Block Lockout Detection.

Chip Erase Operation

The chip-erase mode can be initiated by a six-byte command sequence. After the command loading

cycle, the device enters the internal chip erase mode, which is automatically timed and will be

completed within fast 100 mS (max). The host system is not required to provide any control or timing

during this operation. If the boot block programming lockout is activated, only the data in the other

memory sectors will be erased to FF(hex) while the data in the boot block will not be erased (remains

as the same state before the chip erase operation). The entire memory array will be erased to FF(hex)

by the chip erase operation if the boot block programming lockout feature is not activated. The device

will automatically return to normal read mode after the erase operation completed. Data polling and/or

Toggle Bits can be used to detect end of erase cycle.

Sector/Page Erase Command

Sector/page erase is a six bus cycles operation. There are two "unlock" write cycles, followed by

writing the "set-up" command. Two more "unlock" write cycles then follows by the sector/page erase

command. The sector/page address (any address location within the desired sector/page) is latched

on the falling edge of #WE, while the command (30H/50H) is latched on the rising edge of #WE.

Sector/page erase does not require the user to program the device prior to erase. When erasing a

sector/page or sectors/pages the remaining unselected sectors/pages are not affected. The system is

not required to provide any controls or timings during these operations.

The automatic sector/page erase begins after the erase command is completed, right from the rising

edge of the #WE pulse for the last sector/page erase command pulse and terminates when the data

on DQ7, Data Polling, is "1" at which time the device returns to the read mode. Data Polling must be

performed at an address within any of the sectors/pages being erased.

Refer to the Erase Command flow Chart using typical command strings and bus operations.

Program Operation

The W39V040FA is programmed on a byte-by-byte basis. Program operation can only change logical

data "1" to logical data "0." The erase operation, which changed entire data in main memory and/or

boot block from "0" to "1", is needed before programming.

The program operation is initiated by a 4-byte command cycle (see Command Codes for Byte

Programming). The device will internally enter the program operation immediately after the byte-

program command is entered. The internal program timer will automatically time-out (50

µS max. -

used to detect end of program cycle.