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R5F565N9FDLJ Datasheet(PDF) 7 Page - Renesas Technology Corp |
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R5F565N9FDLJ Datasheet(HTML) 7 Page - Renesas Technology Corp |
7 / 190 page RX65N Group, RX651 Group 1. Overview R01DS0276EJ0100 Rev.1.00 Page 7 of 190 Aug 24, 2016 Communication function I2C bus interface (RIICa) 2 channels (only channel 0 can be used in fast-mode plus) Communication formats I2C bus format/SMBus format Supports the multi-master Max. transfer rate: 1 Mbps (channel 0) Event linking by the ELC CAN module (CAN) 2 channels Compliance with the ISO11898-1 specification (standard frame and extended frame) 32 mailboxes per channel Serial peripheral interface (RSPIc) 3 channel RSPI transfer facility Using the MOSI (master out, slave in), MISO (master in, slave out), SSL (slave select), and RSPCK (RSPI clock) signals enables serial transfer through SPI operation (four lines) or clock-synchronous operation (three lines) Capable of handling serial transfer as a master or slave Data formats Switching between MSB first and LSB first The number of bits in each transfer can be changed to any number of bits from 8 to 16, or to 20, 24, or 32 bits. 128-bit buffers for transmission and reception Up to four frames can be transmitted or received in a single transfer operation (with each frame having up to 32 bits) Transit/receive data can be swapped in byte units Buffered structure Double buffers for both transmission and reception RSPCK can be stopped with the receive buffer full for master reception. Event linking by the ELC Quad serial peripheral interface (QSPI) 1 channel Connectable with serial flash memory equipped with multiple input and output lines (i.e. for single, dual, or quad operation) Programmable bit length and selectable active sense and phase of the clock signal Sequential execution of transfer LSB or MSB first is selectable SD host interface (SDHI)*3 1 channel Transfer speed: Supports high-speed mode (15 MB/s) and default speed mode (11.9 MB/s) One interface for SD memory and I/O cards (supporting 1- and 4-bit SD buses) SD specifications Part 1: Physical Layer Specification Ver.3.01 compliant (DDR not supported) Part E1: SDIO Specification Ver. 3.00 Error checking: CRC7 for commands and CRC16 for data Interrupt requests: Card access interrupt, SDIO access interrupt, card detection interrupt DMA transfer requests: SD_BUF write and SD_BUF read Support for card detection and write protection SD slave interface (SDSI)*3 1 channel Compliant with the SDIO Card Specification Ver.2.00 (CSA is not supported) 1-bit SD/4-bit SD/SPI mode SDIO Proprietary command is supported SD/SPI Mandatory command is supported Interrupt requests: 6 MMC host interface (MMCIF) 1 channel Transfer speed: Data transfer mode (30 MB/s), backward compatible mode (25 MB/s) Compliant with JEDEC STANDARD JESD84-A441 (DDR is not supported) Interface for Multimedia Cards (MMCs) Device buses: Support for 1-, 4-, and 8-bit MMC buses Interrupt requests: Card detection interrupt, error/timeout interrupt, normal operation interrupt DMA transfer requests: CE_DATA write and CE_DATA read Support for card detection, boot operation, high priority interrupt (HPI) Parallel data capture unit (PDC) 1 channel Acquisition of synchronization through external 8-bit horizontal and vertical synchronization signals Setting of the image size when clipping of the output for a one-frame image is required Table 1.1 Outline of Specifications (6/8) Classification Module/Function Description |
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