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PLBG0176GA-A Datasheet(PDF) 6 Page - Renesas Technology Corp |
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PLBG0176GA-A Datasheet(HTML) 6 Page - Renesas Technology Corp |
6 / 228 page RX64M Group 1. Overview R01DS0173EJ0110 Rev.1.10 Page 6 of 228 Oct 24, 2016 Timers General PWM timer (GPTA) 16 bits × 4 channels Counting up or down (saw-wave), counting up and down (triangle-wave) selectable for all channels Four clock sources independently selectable for all channels (PCLKA/1, PCLKA/4, PCLKA/8, PCLKA/16) 2 input/output pins per channel 2 output compare/input capture registers per channel For the 2 output compare/input capture registers of each channel, 4 registers are provided as buffer registers and are capable of operating as comparison registers when buffering is not in use. In output compare operation, buffer switching can be at peaks or troughs, enabling the generation of laterally asymmetrically PWM waveforms. Registers for setting up frame intervals on each channel (with capability for generating interrupts on overflow or underflow) Synchronizable operation of the several counters Modes of synchronized operation (synchronized, or displaced by desired times for phase shifting) Generation of dead times in PWM operation Through combination of three counters, generation of automatic three-phase PWM waveforms incorporating dead times Starting, clearing, and stopping counters in response to external or internal triggers Internal trigger sources: output of the internal comparator detection, software, and compare-match Digital filter function for signals on the input capture and external trigger pins Event linking by the ELC Programmable pulse generator (PPG) (4 bits × 4 groups) × 2 units Pulse output with the MTU or TPU output as a trigger Maximum of 32 pulse-output possible 8-bit timers (TMRb) (8 bits × 2 channels) × 2 units Select from among seven internal clock signals (PCLKB/1, PCLKB/2, PCLKB/8, PCLKB/32, PCLKB/64, PCLKB/1024, PCLKB/8192) and one external clock signal Capable of output of pulse trains with desired duty cycles or of PWM signals The 2 channels of each unit can be cascaded to create a 16-bit timer Generation of triggers for A/D converter conversion Capable of generating baud-rate clocks for SCI5, SCI6, and SCI12 Event linking by the ELC Compare match timer (CMT) (16 bits × 2 channels) × 2 units Select from among four internal clock signals (PCLKB/8, PCLKB/32, PCLKB/128, PCLKB/512) Event linking by the ELC Compare match timer W (CMTW) (32 bits × 1 channel) × 2 units Compare-match, input-capture input, and output-comparison output are available. Select from among four internal clock signals (PCLKB/8, PCLKB/32, PCLKB/128, PCLKB/512) Interrupt requests can be output in response to compare-match, input-capture, and output-comparison events. Event linking by the ELC Realtime clock (RTCd) Clock sources: Main clock, sub clock Selection of the 32-bit binary count in time count/second unit possible Clock and calendar functions Interrupt sources: Alarm interrupt, periodic interrupt, and carry interrupt Battery backup operation Time-capture facility for three values Event linking by the ELC Watchdog timer (WDTA) 14 bits × 1 channel Select from among 6 counter-input clock signals (PCLKB/4, PCLKB/64, PCLKB/128, PCLKB/512, PCLKB/2048, PCLKB/8192) Independent watchdog timer (IWDTa) 14 bits × 1 channel Counter-input clock: IWDT-dedicated on-chip oscillator Dedicated clock/1, dedicated clock/16, dedicated clock/32, dedicated clock/64, dedicated clock/128, dedicated clock/256 Window function: The positions where the window starts and ends are specifiable (the window defines the timing with which refreshing is enabled and disabled). Event linking by the ELC Table 1.1 Outline of Specifications (5/9) Classification Module/Function Description |
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