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R5F563T5EDFM Datasheet(PDF) 5 Page - Renesas Technology Corp

Part # R5F563T5EDFM
Description  100-MHz 32-bit RX MCU, on-chip FPU, 165 DMIPS
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

R5F563T5EDFM Datasheet(HTML) 5 Page - Renesas Technology Corp

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R01DS0087EJ0220 Rev.2.20
Page 5 of 186
Mar 31, 2016
RX63T Group
1. Overview
Timers
General PWM timer
(GPT)
 16 bits x 8 channels
 Counting up or down (saw-wave), counting up and down (triangle-wave) selectable for
all channels
 Select from among four count clocks (PCLKA/1, PCLKA/4, PCLKA/8, and PCLKA/16)
for each channel
 2 input/output pins per channel
 2 output compare/input capture registers per channel
 For the 2 output compare/input capture registers of each channel, 4 registers are
provided as buffer registers and are capable of operating as comparison registers when
buffering is not in use.
 In output compare operation, buffer switching can be at peaks or troughs, enabling the
generation of laterally asymmetrically PWM waveforms.
 Registers for setting up frame intervals on each channel (with capability for generating
interrupts on overflow or underflow)
 Synchronizable operation of the several counters
 Modes of synchronized operation (synchronized, or displaced by desired times for
phase shifting)
 Generation of dead times in PWM operation
 Through combination of three counters, generation of automatic three-phase PWM
waveforms incorporating dead times
 Starting, clearing, and stopping counters in response to external or internal triggers
 Internal trigger sources: Output of the internal comparator detection, software, and
compare-match
 The main clock can be used as a counter clock for measuring the timing of the edges of
signals produced by frequency-dividing the dedicated clock signal for the IWDT (to
detect abnormal oscillation).
 A PWM delay with an accuracy of up to 1/32 times the period of the system clock (ICLK)
can be generated to control the timing with which signals from the two PWM output pins
from each of channels 0 to 3 rise and fall.
Compare match timer
(CMT)
 (16 bits × 2 channels) × 2 units
 Select from among four internal clock signals (PCLK/8, PCLK/32, PCLK/128, PCLK/
512)
Watchdog timer
(WDTA)
 14 bits × 1 channel
 Select from among 6 counter-input clock signals (PCLK/4, PCLK/64, PCLK/128, PCLK/
512, PCLK/2048, PCLK/8192)
Independent watchdog
timer (IWDTa)
 14 bits × 1 channel
 Counter-input clock: Dedicated on-chip oscillator
 Dedicated clock/1, dedicated clock/16, dedicated clock/32, dedicated clock/64,
dedicated clock/128, dedicated clock/256
Communication
function
USB 2.0 host/function
module (USBa)
 Includes a UDC (USB Device Controller) and transceiver for USB 2.0
 Single port
 Compliance with the USB 2.0 specification
 Transfer rate: Full speed (12 Mbps)
 Self-power mode and bus power mode are selectable
 Supports the OTG (On-The-Go)
 Incorporates 2 Kbytes of RAM as a transfer buffer
Serial communications
interfaces (SCIc, SCId)
 5 channels (SCIc: 4 channels + SCId: 1 channel)
 SCIc
Serial communications modes: Asynchronous, clock synchronous, and smart-card
interface
Multi-processor function
On-chip baud rate generator allows selection of the desired bit rate
Choice of LSB-first or MSB-first transfer
Simple I2C
Simple SPI
 SCId (The following functions are added to SCIc)
Supports the serial communications protocol, which contains the start frame and
information frame
Supports the LIN format
Table 1.1
Outline of Specifications (4/7)
Classification
Module/Function
Description


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