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R5F563T5EDFM Datasheet(PDF) 3 Page - Renesas Technology Corp

Part # R5F563T5EDFM
Description  100-MHz 32-bit RX MCU, on-chip FPU, 165 DMIPS
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

R5F563T5EDFM Datasheet(HTML) 3 Page - Renesas Technology Corp

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R01DS0087EJ0220 Rev.2.20
Page 3 of 186
Mar 31, 2016
RX63T Group
1. Overview
Clock
Clock generation circuit
 Main clock oscillator, low-speed on-chip oscillator, PLL frequency synthesizer, and
dedicated on-chip oscillator for the IWDT
 Main-clock oscillation stop detection
 Separate frequency-division and multiplication settings for the system clock (ICLK),
peripheral module clock (PCLKA), peripheral module clock (PCLKB), AD clock
(PCLKC), FlashIF clock (FCLK) and S12AD clock (PCLKD).
The CPU and other bus masters run in synchronization with the system clock (ICLK):
Up to 100 MHz
Multi-function timer pulse unit 3 and general PWM timer run in synchronization with
PCLKA: Up to 100 MHz
Peripheral modules run in synchronization with the peripheral module clock (PCLKB):
Up to 50 MHz
Flash IF run in synchronization with the FlashIF clock (FCLK): Up to 50 MHz
Devices connected to the external bus run in synchronization with the external bus
clock (BCLK): Up to 50 MHz
10-bit A/D converter runs in synchronization with the AD clock (PCLKC): Up to 100 MHz
12-bit A/D converter runs in synchronization with the S12AD clock (PCLKD): Up to 50
MHz
Clock
Clock frequency
accuracy measurement
circuit (CAC)
The frequency of the following clocks can be measured; the main clock oscillator, PLL
circuit, and IWDT-dedicated on-chip oscillator.
Reset
RES# pin reset, power-on reset, voltage-monitoring reset, independent watchdog timer
reset, watchdog timer reset, deep software standby reset, and software reset
Voltage detection circuit
When the voltage on VCC passes the voltage detection level (Vdet), an internal reset or
internal interrupt is generated.
Low power
consumption
Low power
consumption facilities
 Module stop function
 Four low power consumption modes
Sleep mode, all-module clock stop mode, software standby mode, and deep software
standby mode
Interrupt
Interrupt controller
(ICUb)
 Peripheral function interrupts: Up to 169 sources
 External interrupts: Up to 8 (pins IRQ0 to IRQ7)
 Software interrupts: One source
 Non-maskable interrupts: 6 sources
 Sixteen levels specifiable for the order of priority
External bus extension
 The external address space can be divided into four areas (CS0 to CS3), each with
independent control of access settings.
Capacity of each area: 1 Mbyte (CS0 to CS3)
A chip-select signal (CS0# to CS3#) can be output for each area.
Each area is specifiable as an 8- or 16-bit bus space
The data arrangement in each area is selectable as little or big endian (only for data).
 Bus format: Separate bus, multiplex bus
 Wait control
 Write buffer facility
DMA
DMA controller
(DMACA)
 4 channels
 Three transfer modes: Normal transfer, repeat transfer, and block transfer
 Activation sources: Software trigger, external interrupts, and interrupt requests from
peripheral functions
Data transfer controller
(DTCa)
 Three transfer modes: Normal transfer, repeat transfer, and block transfer
 Activation sources: Software interrupt activation register settings, external interrupts,
and interrupt requests from peripheral functions
Table 1.1
Outline of Specifications (2/7)
Classification
Module/Function
Description


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