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RX110 Datasheet(PDF) 72 Page - Renesas Technology Corp

Part # RX110
Description  32 MHz 32-bit RX MCUs, 50 DMIPS
Download  108 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

RX110 Datasheet(HTML) 72 Page - Renesas Technology Corp

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R01DS0202EJ0120 Rev.1.20
Page 72 of 108
Jul 29, 2016
RX110 Group
5. Electrical Characteristics
5.3.5
Timing of On-Chip Peripheral Modules
Note 1. tPcyc: PCLK cycle
Note 2. tcac: CAC count clock source cycle
Note 3. When the LOCO is selected as the clock output source (CKOCR.CKOSEL[2:0] bits = 000b), set the clock output division ratio
selection to divided by 2 (CKOCR.CKODIV[2:0] bits = 001b).
Note 4. When the XTAL external clock input or an oscillator is used with divided by 1 (CKOCR.CKOSEL[2:0] bits = 010b and
CKOCR.CKODIV[2:0] bits = 000b) to output from CLKOUT, the above should be satisfied with an input duty cycle of 45 to 55%.
Table 5.30
Timing of On-Chip Peripheral Modules (1)
Conditions: 1.8 V
≤ VCC ≤ 3.6 V, 1.8 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = 0 V, T
a = –40 to +105°C
Item
Symbol
Min.
Max.
Unit*1
Test
Conditions
I/O ports
Input data pulse width
tPRW
1.5
tPcyc
Figure 5.32
MTU2
Input capture input pulse width
Single-edge setting
tTICW
1.5
tPcyc
Figure 5.33
Both-edge setting
2.5
Timer clock pulse width
Single-edge setting
tTCKWH,
tTCKWL
1.5
tPcyc
Figure 5.34
Both-edge setting
2.5
Phase counting mode
2.5
SCI
Input clock cycle
Asynchronous
tScyc
4—
tPcyc
Figure 5.35
Clock synchronous
6
Input clock pulse width
tSCKW
0.4
0.6
tScyc
Input clock rise time
tSCKr
—20
ns
Input clock fall time
tSCKf
—20
ns
Output clock cycle
Asynchronous
tScyc
16
tPcyc
Figure 5.36
C = 30 pF
Clock synchronous
4
Output clock pulse width
tSCKW
0.4
0.6
tScyc
Output clock rise time
tSCKr
—20
ns
Output clock fall time
tSCKf
—20
ns
Transmit data delay time
(master)
Clock synchronous
tTXD
—40
ns
Transmit data delay time
(slave)
Clock
synchronous
2.7 V or above
65
ns
1.8 V or above
100
ns
Receive data setup time
(master)
Clock
synchronous
2.7 V or above
tRXS
65
ns
1.8 V or above
90
ns
Receive data setup time
(slave)
Clock synchronous
40
ns
Receive data hold time
Clock synchronous
tRXH
40
ns
A/D
converter
Trigger input pulse width
tTRGW
1.5
tPcyc
Figure 5.37
CAC
CACREF input pulse width
tPcyc ≤ tcac*2
tCACREF
4.5 tcac + 3 tPcyc
—ns
tPcyc > tcac*2
5 tcac + 6.5 tPcyc
CLKOUT
CLKOUT pin output cycle*4
VCC = 2.7 V or above
tCcyc
125
ns
VCC = 1.8 V or above
250
CLKOUT pin high pulse width*3
VCC = 2.7 V or above
tCH
35
ns
VCC = 1.8 V or above
70
CLKOUT pin low pulse width*3
VCC = 2.7 V or above
tCL
35
ns
VCC = 1.8 V or above
70
CLKOUT pin output rise time
VCC = 2.7 V or above
tCr
—15
ns
VCC = 1.8 V or above
30
CLKOUT pin output fall time
VCC = 2.7 V or above
tCf
—15
ns
VCC = 1.8 V or above
30


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