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S5D9 Datasheet(PDF) 63 Page - Renesas Technology Corp |
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S5D9 Datasheet(HTML) 63 Page - Renesas Technology Corp |
63 / 115 page R01DS0303EU0100 Rev.1.00 Page 63 of 115 Nov 3, 2016 S5D9 2. Electrical Characteristics Note 1. tPBcyc: PCLKB cycle. Note 2. tcac: CAC count clock source cycle. 2.3.10 SCI Timing Note 1. tPcyc: PCLKA cycle. Figure 2.39 SCK clock input/output timing Table 2.22 SCI timing (1) Conditions: High drive output is selected in the port drive capability bit in the PmnPFS register for the following pins: SCK0 to SCK9. For other pins, middle drive output is selected in the port drive capability bit in the PmnPFS register. Item Symbol Min Max Unit*1 Test conditions SCI Input clock cycle Asynchronous tScyc 4 - tPcyc Figure 2.39 Clock synchronous 6- Input clock pulse width tSCKW 0.4 0.6 tScyc Input clock rise time tSCKr -5 ns Input clock fall time tSCKf -5 ns Output clock cycle Asynchronous tScyc 6- tPcyc Clock synchronous 4- Output clock pulse width tSCKW 0.4 0.6 tScyc Output clock rise time tSCKr -5 ns Output clock fall time tSCKf -5 ns Transmit data delay Clock synchronous tTXD -25 ns Figure 2.40 Receive data setup time Clock synchronous tRXS 15 - ns Receive data hold time Clock synchronous tRXH 5- ns tSCKW tSCKr tSCKf tScyc SCKn (n = 0 to 9) |
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