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R7FS124773A01CNB Datasheet(PDF) 2 Page - Renesas Technology Corp |
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R7FS124773A01CNB Datasheet(HTML) 2 Page - Renesas Technology Corp |
2 / 98 page R01DS0264EU0100 Rev.1.00 Page 2 of 95 Feb 23, 2016 S124 1. Overview 1. Overview The S124 MCU comprises multiple series of software- and pin-compatible ARM-based 32-bit MCUs that share a common set of Renesas peripherals to facilitate design scalability and efficient platform-based product development. Based on the energy-efficient ARM® Cortex®-M0+ 32-bit core, this MCU is particularly well suited for cost-sensitive and low-power applications. The MCU in this series feature: Up to 128 KB code flash memory 16-KB SRAM Capacitive Touch Sensing Unit (CTSU) 14-bit ADC 12-bit DAC Security features. 1.1 Function Outline Table 1.1 ARM core Feature Functional description ARM Cortex-M0+ Maximum operating frequency: up to 32 MHz ARM Cortex-M0+: - Revision: r0p1-00rel0 - ARMv6-M architecture profile - Single-cycle integer multiplier. SysTick timer - Driven by LOCO clock. Table 1.2 Memory Feature Functional description Code flash memory Maximum 128 KB code flash memory. See section 37, Flash Memory in User's Manual. Data flash memory 4 KB data flash memory. See section 37, Flash Memory in User's Manual. Option-Setting Memory The option-setting memory determines the state of the MCU after a reset. See section 6, Option-Setting Memory and Information Memory in User's Manual. SRAM The MCU has an on-chip high-speed SRAM with even parity bit. See section 36, SRAM in User's Manual. Table 1.3 System (1/2) Feature Functional description Operating mode Two operating modes: Single-chip mode SCI boot mode. See section 3, Operating Modes in User's Manual. Reset The MCU has 9 types of resets: RES pin reset Power-on reset Independent watchdog timer reset Watchdog timer reset Voltage monitor 0 reset Voltage monitor 1 reset Voltage monitor 2 reset SRAM parity error reset Software reset. See section 5, Resets in User's Manual. |
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