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UPD48288209AF1 Datasheet(PDF) 45 Page - Renesas Technology Corp |
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UPD48288209AF1 Datasheet(HTML) 45 Page - Renesas Technology Corp |
45 / 54 page µµµµPD48288209AF1, µµµµPD48288218AF1, µµµµPD48288236AF1 R10DS0254EJ0101 Rev. 1.01 Page 45 of 53 Jan. 15, 2016 Table 3-3. JTAG AC Characteristics (0°C ≤≤≤≤ TC ≤≤≤≤ 95°C) Parameter Symbol Conditions MIN. MAX. Unit Note Clock Clock cycle time tTHTH 20 ns Clock frequency fTF 50 MHz Clock HIGH time tTHTL 10 ns Clock LOW time tTLTH 10 ns Output time TCK LOW to TDO unknown tTLOX 0 ns TCK LOW to TDO valid tTLOV 10 ns Setup time TMS setup time tMVTH 5 ns TDI valid to TCK HIGH tDVTH 5 ns Capture setup time tCSJ 5 ns 1 Hold time TMS hold time tTHMX 5 ns TCK HIGH to TDI invalid tTHDX 5 ns Capture hold time tCHJ 5 ns 1 Note tCSJ and tCHJ refer to the setup and hold time requirements of latching data from the boundary scan register. JTAG Timing Diagram tTHTH tTLOV tTLTH tTHTL tMVTH tTHDX tDVTH tTHMX TCK TMS TDI TDO tTLOX |
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