mD48576236F1-E24-DW1-A datasheet(1/54 Pages) RENESAS

Part #	mD48576236F1-E24-DW1-A

Description	576M-BIT Low Latency DRAM

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Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

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R10DS0256EJ0101 Rev. 1.01

Page 1 of 53

Jan. 15, 2016

Datasheet

µµµµPD48576209F1

µµµµPD48576218F1

µµµµPD48576236F1

576M-BIT Low Latency DRAM

Common I/O

Description

The

µPD48576209F1 is a 67,108,864-word by 9 bit, the µPD48576218F1 is a 33,554,432 word by 18 bit and the

µPD48576236F1 is a 16,777,216 word by 36 bit synchronous double data rate Low Latency RAM fabricated with

advanced CMOS technology using one-transistor memory cell.

The

µPD48576209F1, µPD48576218F1 and µPD48576236F1 integrate unique synchronous peripheral circuitry and a

burst counter. All input registers controlled by an input clock pair (CK and CK#) are latched on the positive edge of CK

and CK#. These products are suitable for application which require synchronous operation, high speed, low voltage,

high density and wide bit configuration.

Specification

• Density: 576M bit

• Organization

-

Common I/O: 8M words x 9 bits x 8 banks

4M words x 18 bits x 8 banks

2M words x 36 bits x 8 banks

• Operating frequency: 533 / 400 / 300 MHz

• Interface: HSTL I/O

• Package: 144-pin FBGA

-

Package size: 18.5 x 11

-

Lead free

• Power supply

-

2.5 V VEXT

-

1.8 V VDD

-

1.5 V or 1.8 V VDDQ

• Refresh command

-

Auto Refresh

-

16K cycle / 32 ms for each bank

-

128K cycle / 32 ms for total

• Operating case temperature : Tc = 0 to 95°C

Features

• SRAM-type interface

• Double-data-rate architecture

• PLL circuitry

• Cycle time:

1.875 ns @ tRC = 15 ns

2.5 ns @ tRC = 15 ns

2.5 ns @ tRC = 20 ns

3.3 ns @ tRC = 20 ns

• Non-multiplexed addresses

• Multiplexing option is available.

• Data mask for WRITE commands

• Differential input clocks (CK and CK#)

• Differential input data clocks (DK and DK#)

• Data valid signal (QVLD)

• Programmable burst length: 2 / 4 / 8 (x9 / x18 / x36)

• User programmable impedance output (25 Ω - 60 Ω)

• JTAG boundary scan

R10DS0256EJ0101

Rev. 1.01

Jan. 15, 2016

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