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HT56R22 Datasheet(PDF) 78 Page - Holtek Semiconductor Inc |
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HT56R22 Datasheet(HTML) 78 Page - Holtek Semiconductor Inc |
78 / 127 page HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 Rev. 1.30 78 December 26, 2014 · SPICTL1 Register Bit 76543210 Name ¾¾ CKPOL1 CKEG1 MLS1 CSEN1 WCOL1 TRF1 R/W ¾¾ R/W R/W R/W R/W R/W R/W POR 00000000 Bit 7~6 unimplemented, read as ²0² Bit 5 CKPOL1: Determines the base condition of the clock line 0: SCK1 line high when the clock is inactive 1: SCK1 line low when the clock is inactive The CKPOL1 bit determines the base condition of the clock line, if the bit is high, then the SCK1 line will be low when the clock is inactive. When the CKPOL1 bit is low, then the SCK1 line will be high when the clock is inactive. Bit 4 CKEG1: Determines the SPI1 SCK1 active clock edge type CKPOL1=0: 0: SCK1 has high base level with data capture on SCK1 rising edge 1: SCK1 has high base level with data capture on SCK1 falling edge CKPOL1=1: 0: SCK1 has low base level with data capture on SCK1 falling edge 1: SCK1 has low base level with data capture on SCK1 rising edge The CKEG1 and CKPOL1 bits are used to setup the way that the clock signal outputs and inputs data on the SPI bus. These two bits must be configured before a data transfer is executed otherwise an erroneous clock edge may be generated. The CKPOL1 bit determines the base condition of the clock line, if the bit is high, then the SCK1 line will be low when the clock is inactive. When the CKPOL1 bit is low, then the SCK1 line will be high when the clock is inactive. The CKEG1 bit determines active clock edge type which depends upon the condition of CKPOL1 bit. Bit 3 MLS1: Determines the data shift order - MSB or LSB 0: LSB transmitted first 1: MSB transmitted first Bit 2 CSEN1: SPI1 bus select 0: Disable - SPI1 bus is floating 1: Enable Bit 1 WCOL1: Write collision flag 0: Collision free 1: Collision detected This flag is set by the by the SPI1 bus and cleared by the application program. The flag will be set to 1 if data is written to the SPIDR register (TXRX buffer) when a data is still being transferred. Any such data write actions will be ignored in such cases. Bit 0 TRF1: Transmit/Receive completion flag 0: Not complete 1: Data Transmission/Reception Complete This flag will be set high when a data reception or transmission has completed. It must be cleared using the application program and can be used to generate an interrupt. |
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Similar Description - HT56R22_14 |
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