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HT56R22 Datasheet(PDF) 80 Page - Holtek Semiconductor Inc |
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HT56R22 Datasheet(HTML) 80 Page - Holtek Semiconductor Inc |
80 / 127 page HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 Rev. 1.30 80 December 26, 2014 SPI Configuration Options A configuration option is provided for an overall on/off control for the SPI bus. Additional configuration options are provided to enable operation of the WCOL1 bit which is the write collision bit and the CSEN1 bus select bit. Peripheral Clock Output The Peripheral Clock Output allows the device to supply external hardware with a clock signal synchronised to the microcontroller clock. Peripheral Clock Operation As the peripheral clock output pin, PCK, is shared with an I/O line, the required pin function is chosen via PCKEN in the SIMC0 register. The Peripheral Clock function is controlled using the SIMC0 register. The clock source for the Peripheral Clock Output can origi- nate from either the Timer/Event Counter 0 or a divided ratio of the internal fSYS clock. The PCKEN bit in the SIMC0 register is the overall on/off control, setting PCKEN bit to 1 enables the Peripheral Clock, setting PCKEN bit to 0 disables it. The required division ratio of the system clock is selected using the PCKP1 and PCKP0 bits in the same register. If the device enters the SLEEP Mode this will disable the Peripheral Clock out- put. · SIMC0 Register Bit 76543210 Name SIM2 SIM1 SIM0 PCKEN PCKP1 PCKP0 SIMEN ¾ R/W R/W R/W R/W R/W R/W R/W R/W ¾ POR 1110000 ¾ Bit 7~5 SIM2, SIM1, SIM0: SIM operating mode control described in SIM section Bit 4 PCKEN: PCK output pin control 0: Disable 1: Enable Bit 3~2 PCKP1, PCKP0: select PCK output pin frequency 00: fSYS 01: fSYS/4 10: fSYS/8 11: TM0 CCRP match frequency/2 Bit 1 SIMEN: SIM control described in SIM section Bit 0 unimplemented, read as ²0² |
Similar Part No. - HT56R22_14 |
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Similar Description - HT56R22_14 |
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