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HT56R22 Datasheet(PDF) 83 Page - Holtek Semiconductor Inc |
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HT56R22 Datasheet(HTML) 83 Page - Holtek Semiconductor Inc |
83 / 127 page HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 Rev. 1.30 83 December 26, 2014 Interrupts Interrupts are an important part of any microcontroller system. When an external event or an internal function such as a Timer/Event Counter or Time Base requires microcontroller attention, their corresponding interrupt will enforce a temporary suspension of the main pro- gram allowing the microcontroller to direct attention to their respective needs. The devices contain a single external interrupt and mul- tiple internal interrupts. Interrupt Register Overall interrupt control, which means interrupt en- abling and request flag setting, is controlled by using several registers, INTC0, INTC1, MFIC0 and MFIC1. By controlling the appropriate enable bits in this registers each individual interrupt can be enabled or disabled. Also when an interrupt occurs, the corresponding re- quest flag will be set by the microcontroller. The global enable flag if cleared to zero will disable all interrupts. Interrupt Operation A range of internal and external events can all generate an interrupt, by setting their correspponding request flag, if their appropriate interrupt enable bit is set. When this happens, the Program Counter, which stores the address of the next instruction to be executed, will be transferred onto the stack. The Program Counter will then be loaded with a new address which will be the value of the corresponding interrupt vector. The microcontroller will then fetch its next instruction from this interrupt vector. The instruction at this vector will usually be a JMP statement which will jump to another section of program which is known as the interrupt ser- vice routine. Here is located the code to control the ap- propriate interrupt. The interrupt service routine must be terminated with a RETI instruction, which retrieves the original Program Counter address from the stack and al- lows the microcontroller to continue with normal execu- tion at the point where the interrupt occurred. The various interrupt enable bits, together with their as- sociated request flags, are shown in the following dia- gram with their order of priority. Once an interrupt subroutine is serviced, all the other in- terrupts will be blocked, as the EMI bit will be cleared au- tomatically. This will prevent any further interrupt nesting from occurring. However, if other interrupt re- quests occur during this interval, although the interrupt will not be immediately serviced, the request flag will still be recorded. If an interrupt requires immediate servicing while the program is already in another interrupt service routine, the EMI bit should be set after entering the rou- tine, to allow interrupt nesting. If the stack is full, the in- terrupt request will not be acknowledged, even if the related interrupt is enabled, until the Stack Pointer is decremented. If immediate service is desired, the stack must be prevented from becoming full. When an interrupt request is generated it takes 2 or 3 in- struction cycle before the program jumps to the interrupt vector. If the device is in the Sleep or Idle Mode and is woken up by an interrupt request then it will take 3 cy- cles before the program jumps to the interrupt vector. Wait for 2 ~ 3 Instruction Cycles Main Program ISR Entry Enable Bit Set ? Main Program RETI (it will set EMI automatically) Automatically Disable Interrupt Clear EMI & Request Flag Interrupt Request or Interrupt Flag Set by Instruction Y N Interrupt Flow |
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