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NAU82028 Datasheet(PDF) 11 Page - List of Unclassifed Manufacturers |
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NAU82028 Datasheet(HTML) 11 Page - List of Unclassifed Manufacturers |
11 / 19 page NAU82028 Datasheet Rev0.2 Page 11 of 19 Mar, 2013 5.1.1 2-Wire-Serial Control and Data Bus (I 2C Style Interface) The serial interface provides a 2-wire bidirectional read/write data interface similar to and typically compatible with standard I2C protocol. This protocol defines any device that sends CLK onto the bus as a master, and the receiving device as slave. The NAU82028 can function only as a slave device. An external clock drives the device, and in accordance with the protocol, data is sent to or from the device accordingly. All functions are controlled by means of a register control interface in the device. 5.1.2 2-Wire Protocol Convention All 2-Wire interface operations must begin with a START condition, which is a HIGH-to-LOW transition of SDA while SCL is HIGH. All 2-Wire interface operations are terminated by a STOP condition, which is a LOW to HIGH transition of SDA while SCL is HIGH. A STOP condition at the end of a read or write operation places the serial interface in standby mode. An acknowledge (ACK), is a software convention is used to indicate a successful data transfer. The transmitting device releases the SDA bus after transmitting eight bits to allow for the ACK response. During the ninth clock cycle, the receiver pulls the SDA line LOW to acknowledge the reception of the eight bits of data. Following a START condition, the master must output a device address byte. This consists of a 7-bit device address, and the LSB of the device address byte is the R/W (Read/Write) control bit. When R/W= 1, this indicates the master is initiating a read operation from the slave device, and when R/W=0, the master is initiating a write operation to the slave device. If the device address matches the address of the slave device, the slave will output an ACK during the period when the master allows for the ACK signal. STOP SCL SDA START START and STOP signals 9 8 1 2 ...7 Acknowledge SCL SDA Not Acknowledge Acknowledge and NOT Acknowledge Device Address Byte Control Address Byte Data Byte 0 1 0 1 0 1 0 R/W A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Slave Address Byte, Control Address Byte, and Data Byte |
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Similar Description - NAU82028 |
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