N575F145 datasheet(9/21 Pages) ETC2

Part #	N575F145

Description	system-on-chip product

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N575F145 Data Sheet

Release Date: Sep. 2015

- 9 -

Version A1.1

Pin Name

Pin Type

Alt CFG

Description

VCCSPK

P

Power Supply for PWM Speaker Driver

RESETN

I

External reset input. Pull this pin low to reset device to

initial state. Has internal weak pull-up.

ICE_DAT

I/O

Serial Wire Debug port data pin. Has internal weak pull-

up.

ICE_CLK

I

Serial Wire Debug port clock pin. Has internal weak pull-

up.

VSSD

P

Digital Ground.

PA.7

I/O

0

General purpose input/output pin; Port A, bit 7

I

2S_SDO

O

1

Serial Data Out for I

2S interface

PA.6

I/O

0

General purpose input/output pin; Port A, bit 6

I

2S_SDI

I

1

Serial Data In for I

2S interface

PA.5

I/O

0

General purpose input/output pin; Port A, bit 5

I

2S_BCLK

I/O

1

Bit Clock for I

2S interface

PA.4

I/O

0

General purpose input/output pin; Port A, bit 4

I

2S_FS

I/O

1

Frame Sync Clock for I

2S interface

PA.3

I/O

0

General purpose input/output pin; Port A, bit 3

SPI_MISO0

I

1

Master In, Slave Out channel 0 for SPI interface

I

2C_SDA

I/O

2

Serial Data, I

2C interface

PA.2

I/O

0

General purpose input/output pin; Port A, bit 2

SPI_SSB0

I/O

1

Slave Select Bar 0 for SPI interface

VDD33

P

LDO Regulator Output. If used, a 1µF capacitor must be

placed to ground. If not used then tie to VCCD.

PA.1

I/O

0

General purpose input/output pin; Port A, bit 1

SPI_SCLK

I/O

1

Serial Clock for SPI interface

I

2C_SCL

I/O

2

Serial Clock, I

2C interface

PA.0

I/O

0

General purpose input/output pin; Port A, bit 2

SPI_MOSI0

O

1

Master Out, Slave In channel 0 for SPI interface

MCLK

O

2

Master clock output.

VCCLDO

P

Power Supply for LDO, should be connected to VCCD

PA.14

I/O

0

General purpose input/output pin; Port A, bit 14

SDCLK

O

1

Clock output for digital microphone mode.

SDCLKn

O

2

Inverse Clock output for digital microphone mode.

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