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WM8775 Datasheet(PDF) 9 Page - Cirrus Logic |
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WM8775 Datasheet(HTML) 9 Page - Cirrus Logic |
9 / 39 page Production Data WM8775 w PD, Rev 4.4, October 2008 9 DIGITAL AUDIO INTERFACE – SLAVE MODE BCLK DOUT ADCLRC WM8775 ADC DVD Controller Figure 4 Audio Interface – Slave Mode BCLK ADCLRC t BCH t BCL t BCY DOUT t LRSU t LRH t DD Figure 5 Digital Audio Data Timing – Slave Mode Test Conditions AVDD = 5V, DVDD = 3.3V, AGND = 0V, DGND = 0V, TA = +25 oC, Slave Mode, fs = 48kHz, MCLK = 256fs unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Audio Data Input Timing Information BCLK cycle time tBCY 50 ns BCLK pulse width high tBCH 20 ns BCLK pulse width low tBCL 20 ns ADCLRC set-up time to BCLK rising edge tLRSU 10 ns ADCLRC hold time from BCLK rising edge tLRH 10 ns DOUT propagation delay from BCLK falling edge tDD 0 10 ns Table 3 Digital Audio Data Timing – Slave Mode Note: ADCLRC should be synchronous with MCLK, although the WM8775 interface is tolerant of phase variations or jitter on these signals. |
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