AT91M43300

6

EBI: External Bus Interface

The EBI generates the signals that control the access to

the external memory or peripheral devices. The EBI is fully

programmable and can address up to 64M bytes. It has

eight chip selects and a 24-bit address bus, the upper four

bits of which are multiplexed with a chip select.

The 16-bit data bus can be configured to interface with 8-

or 16-bit external devices. Separate read and write control

signals allow for direct memory and peripheral interfacing.

The EBI supports different access protocols, allowing sin-

gle-clock-cycle memory accesses.

The main features are:

•

External memory mapping

•

Up to eight chip select lines

•

8- or 16-bit data bus

•

Byte-write or byte-select lines

•

Remap of boot memory

•

Two different read protocols

•

Programmable wait state generation

•

External wait request

•

Programmable data float time

AIC: Advanced Interrupt Controller

The AT91M43300 has an 8-level priority, individually-

maskable, vectored interrupt controller. This feature sub-

stantially reduces the software and real-time overhead in

handling internal and external interrupts.

The interrupt controller is connected to the NFIQ (fast inter-

rupt request) and the NIRQ (standard interrupt request)

inputs of the ARM7TDMI processor. The processor’s NFIQ

line can only be asserted by the external fast interrupt

request input: FIQ. The NIRQ line can be asserted by the

interrupts generated by the on-chip peripherals and the

external interrupt request lines: IRQ0 to IRQ3.

An 8-level priority encoder allows the customer to define

the priority between the different NIRQ interrupt sources.

Internal sources are programmed to be level sensitive or

edge triggered. External sources can be programmed to be

positive- or negative-edge triggered or high- or low-level

sensitive.

PIO: Parallel I/O Controller

The AT91M43300 features 58 programmable I/O lines. 14

pins on the AT91M43300 are dedicated as general-pur-

pose I/O pins. Other I/O lines are multiplexed with on-chip

peripheral I/O signals in order to optimize the use of avail-

able package pins. The I/O lines are controlled by two sep-

arate and identical PIO controllers (PIOA and PIOB). Each

PIO controller also provides an internal interrupt signal to

the Advanced Interrupt Controller (AIC).

USART: Universal

Synchronous/Asynchronous

Receiver/Transmitter

The AT91M43300 provides three identical, full-duplex, uni-

versal synchronous/asynchronous receiver/transmitters

that interface to the APB and are connected to the Periph-

eral Data Controller.

The main features are:

•

Programmable baud rate generator

•

Parity, framing and overrun error detection

•

Line break generation and detection

•

Automatic echo, local loopback and remote loopback

channel modes

•

Multi-drop mode: address detection and generation

•

Interrupt generation

•

Two dedicated Peripheral Data Controller channels

•

5-, 6-, 7-, 8- and 9-bit character length

SPI: Serial Peripheral Interface

The AT91M43300 features an SPI that provides communi-

cation with external devices in master or slave mode.

The SPI has four external chip selects that can be con-

nected to up to 15 devices. The data length is programma-

ble, from 8- to 16-bit.

As for the USART, a two-channel PDC is used to move

data directly between memory and the SPI without CPU

intervention for maximum real-time processing throughput.

TC: Timer/Counter

The AT91M43300 features two identical timer/counter

blocks, each containing three identical 16-bit timer/counter

channels. Each channel can be independently pro-

grammed to perform a wide range of functions, including

frequency measurement, event counting, interval measure-

ment, pulse generation, delay timing and pulse width mod-

ulation.

Each timer/counter channel has three external clock inputs,

five internal clock inputs, and two multi-purpose input/out-

put signals which can be configured by the user. Each

channel drives an internal interrupt signal which can be

programmed to generate processor interrupts via the

Advanced Interrupt Controller (AIC).

Each timer/counter block features two global registers that

act upon all three TC channels. The Block Control Register

allows the three channels to be started simultaneously with

the same instruction. The Block Mode Register defines the

external clock inputs for each timer/counter channel, allow-

ing them to be chained.