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CPS-1432 Datasheet(PDF) 7 Page - Integrated Device Technology |
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CPS-1432 Datasheet(HTML) 7 Page - Integrated Device Technology |
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7 / 79 page  7 ©2017 Integrated Device Technology, Inc. June 26, 2017 CPS-1432 Datasheet Specification Compliancy • RapidIO Specification (Rev. 2.1), Part 1: Input/Output Logical Specification, 08/2009, RTA • RapidIO Specification (Rev. 2.1), Part 2: Message Passing Logical Specification, 08/2009, RTA • RapidIO Specification (Rev. 2.1), Part 3: Common Transport Specification, 08/2009, RTA • RapidIO Specification (Rev. 2.1), Part 6: LP-Serial Physical Layer Specification, 08/2009, RTA • RapidIO Specification (Rev. 2.1), Part 7: System and Device Interoperability Specification, 08/2009, RTA • RapidIO Specification (Rev. 2.1), Part 8: Error Management Extensions Specification, 08/2009, RTA • RapidIO Specification (Rev. 2.1), Part 9: Flow Control Logic Layer Extensions Specification, 08/2009, RTA • RapidIO Specification (Rev. 2.1), Part 11: Multicast Extensions Specification, 08/2009, RTA • RapidIO Specification (Rev. 2.1), Annex I: Software/System Bring Up Specification, 08/2009, RTA • IEEE Std 1149.1-2001 IEEE Standard Test Access Port and Boundary-Scan Architecture • IEEE Std 1149.6-2003 IEEE Standard for Boundary-Scan Testing of Advanced Digital Networks • The I2C-BUS Specification (v 2.1), January 2000, Philips 3. Functional Overview The CPS-1432 is optimized for line card and backplane switching. Its primary function is to switch data plane and control plane data packets using S-RIO between a set of devices that reside on the same line card. In addition, it can bridge communications between multiple on-board (or local) devices and a set of external line cards by providing long run RapidIO backplane interconnects. In this manner, for example, the device can serve as a switch between a set of RF cards and a set of RapidIO based DSPs in a wireless basestation. The CPS-1432 supports packet switching from its 14 RapidIO ports. Packets can be unicast, multicast, or broadcast. The encoded data rate for each of the lanes are configurable to either 1.25, 2.5, 3.125, 5, or 6.25 Gbaud. The device supports lane groupings such that 1x, 2x, and 4x operation is provided, as defined in the RapidIO Specification (Rev. 2.1). The CPS-1432 supports the reception of S-RIO maintenance packets (type 8) which are directed to it (that is, a hop count of 0). The device can properly process and forward received maintenance packets with a hop count > 0 as defined in the RapidIO Specification (Rev. 2.1). With the exception of maintenance packets, received packets are transmitted unmodified. The CPS-1432 supports four priority levels plus Critical Request Flow (CRF), as defined in the RapidIO Specification (Rev. 2.1), Part 6. It is programmable by all of the following: S-RIO ports, I2C, and JTAG Interface. From a switching perspective the CPS-1432 functions statically. As such, all input to output port mappings are configurable through registers. Unless register configurations are changed, the input to output mappings remains static regardless of the received data. The switching functionality does not dynamically “learn” which destIDs are tied to a port endpoint by examining S-RIO header fields and dynamically updating internal routing tables. The CPS-1432 supports “Store and Forward” or “Cut-Through” packet forwarding (for more information, see the “Switch Fabric” chapter in the CPS-1432 User Manual). |
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