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AC Loading and Waveforms

Note: The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and LVTTL/CMOS I/O. Depending on the valid strobe edge of

transmitter, the TxCLKIn can be either rising or falling edge data strobe.

FIGURE 3. “Worst Case” Test Pattern

FIGURE 4. Transmitter LVDS Output Load and Transition Times

FIGURE 5. Receiver LVTTL/CMOS Output Load and Transition Times

FIGURE 6. Transmitter Setup/Hold and HIGH/LOW Times (Rising Edge Strobe)

FIGURE 7. Transmitter Input Clock Transition Time