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ICS950902YFLF-T Datasheet(PDF) 1 Page - Integrated Circuit Systems

Part # ICS950902YFLF-T
Description  Programmable Timing Control Hub??for P4?
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Manufacturer  ICST [Integrated Circuit Systems]
Direct Link  http://www.icst.com
Logo ICST - Integrated Circuit Systems

ICS950902YFLF-T Datasheet(HTML) 1 Page - Integrated Circuit Systems

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Integrated
Circuit
Systems, Inc.
ICS950902
0475G—03/23/04
Pin Configuration
Recommended Application:
VIA P4X/P4M/KT/KN266/333 style chipsets.
Output Features:
•
1 - Pair of differential CPU clocks @ 3.3V (CK408)/
1 - Pair of differential open drain CPU clocks (K7)
•
1 - Pair of differential push pull CPU_CS clocks @ 2.5V
•
3 - AGP @ 3.3V
•
7 - PCI @ 3.3V (1 - Free running)
•
1 - 48MHz @ 3.3V fixed
•
1 - 24_48MHz @ 3.3V (Default 48MHz I
2C select only)
•
2 - REF @ 3.3V, 14.318MHz
•
12 - SDRAM (6 pair - DDR) selectable
Key Specifications:
•
CPU_CS - CPUT/C: <±250ps
•
CPU_CS - AGP: <±250ps
•
CPU - DDR/SD: <±250ps
•
PCI - PCI: <500ps
•
CPU - PCI: Min = 1.0ns, Typ = 2.0ns, Max = 4.0ns
Programmable Timing Control Hub™ for P4™
* Internal 120K pull-up resistor to VDD.
** Internal 120K pull-down resistor to GND.
56-Pin 300-mil SSOP & 240-mil TSSOP
Frequency Table
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*FS0/REF0 1
56 Vtt_PWRGD#**/REF1
GND 2
55 VDDREF
X1 3
54 GND
X2 4
53 CPUCLKT/CPUCLKODT
VDDAGP 5
52 CPUCLKC/CPUCLKODC
*MODE/AGPCLK0 6
51 VDDCPU3.3
*SEL_408/K7/AGPCLK1 7
50 VDDCPU2.5
*(PCI_STOP#)AGPCLK2 8
49 CPUC_CS
GNDAGP 9
48 CPUT_CS
**FS1/PCICLK_F 10
47 GND
**SEL_SDR/DDR#/PCICLK1 11
46 FBOUT
*MULTSEL/PCICLK2 12
45 BUF_IN
GNDPCI 13
44 DDRT0/SDRAM0
PCICLK3 14
43 DDRC0/SDRAM1
PCICLK4 15
42 DDRT1/SDRAM2
VDDPCI 16
41 DDRC1/SDRAM3
PCICLK517
40VDD3.3_2.5
*(CLK_STOP#)PCICLK6 18
39 GND
GND48 19
38 DDRT2/SDRAM4
*FS3/48MHz 20
37 DDRC2/SDRAM5
*FS2/24_48MHz 21
36 DDRT3/SDRAM6
AVDD48 22
35 DDRC3/SDRAM7
VDD 23
34 VDD3.3_2.5
GND 24
33 GND
IREF 25
32 DDRT4/SDRAM8
*(PD#)RESET# 26
31 DDRC4/SDRAM9
SCLK 27
30 DDRT5/SDRAM10
SDATA 28
29 DDRC5/SDRAM11
Features/Benefits:
•
Programmable output frequency.
•
Programmable output divider ratios.
•
Programmable output rise/fall time.
•
Programmable output skew.
•
Programmable spread percentage for EMI control.
•
DDR output buffer supports up to 200MHz.
•
Watchdog timer technology to reset system
if system malfunctions.
•
Programmable watch dog safe frequency.
•
Support I
2C Index read/write and block read/write
operations.
•
Uses external 14.318MHz crystal.


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