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ICS954201YFLNT Datasheet(PDF) 6 Page - Integrated Circuit Systems |
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ICS954201YFLNT Datasheet(HTML) 6 Page - Integrated Circuit Systems |
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6 / 10 page  6 Integrated Circuit Systems, Inc. ICS954201 0819G—12/06/04 Absolute Max Symbol Parameter Min Max Units VDD_A 3.3V Core Supply Voltage VDD + 0.5V V VDD_In 3.3V Logic Input Supply Voltage GND - 0.5 VDD + 0.5V V Ts Storage Temperature -65 150 °C Tambient Ambient Operating Temp 0 70 °C Tcase Case Temperature 115 °C ESD prot Input ESD protection human body model 2000 V Electrical Characteristics - Input/Supply/Common Output Parameters TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5% PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Notes Input High Voltage VIH 3.3 V +/-5% 2 VDD + 0.3 V 1 Input Low Voltage VIL 3.3 V +/-5% VSS - 0.3 0.8 V 1 Input High Current IIH VIN = VDD -5 5 uA 1 IIL1 VIN = 0 V; Inputs with no pull-up resistors -5 uA 1 IIL2 VIN = 0 V; Inputs with pull-up resistors -200 uA 1 Low Threshold Input High Voltage VIH_FS 3.3 V +/-5% 0.7 VDD + 0.3 V 1 Low Threshold Input Low Voltage VIL_FS 3.3 V +/-5% VSS - 0.3 0.35 V 1 Operating Supply Current IDD3.3OP Full Active, CL = Full load; 278 400 mA all diff pairs driven 67 70 mA all differential pairs tri-stated 4.8 12 mA Input Frequency 3 Fi VDD = 3.3 V 14.31818 MHz 3 Pin Inductance 1 Lpin 7nH 1 CIN Logic Inputs 5 pF 1 COUT Output pin capacitance 6 pF 1 CINX X1 & X2 pins 5 pF 1 Clk Stabilization 1,2 TSTAB From VDD Power-Up or de- assertion of PD# to 1st clock 1.3 1.8 ms 1,2 Modulation Frequency Triangular Modulation 30 33 kHz 1 Tdrive_SRC SRC output enable after PCI_STOP de-assertion 810 ns 1 Tdrive_PD Differential output enable after PD# de-assertion 300 us 1 Tfall_PD PD# fall time of 5 ns 1 Trise_PD PD# rise time of 5 ns 2 Tdrive_CPU_STOP CPU output enable after CPU_STOP de-assertion 810 ns 1 Tfall_CPU_STOP CPU_STOP fall time of 5 ns 1 Trise_CPU_STOP# CPU_STOP rise time of 5 ns 2 SMBus Voltage VDD 2.7 5.5 V 1 Low-level Output Voltage VOL SDATA, SCLK @ IPULLUP 0.4 V 1 Current sinking IPULLUP VOL = 0.4 V 4 mA 1 SCLK/SDATA Clock/Data Rise Time TRI2C (Max VIL - 0.15) to (Min VIH + 0.15) 1000 ns 1,3 SCLK/SDATA Clock/Data Fall Time TFI2C (Min VIH + 0.15) to (Max VIL - 0.15) 300 ns 1,3 1Guaranteed by design, not 100% tested in production. 2See timing diagrams for timing requirements. 3 Input frequency should be measured at the REF output pin and tuned to ideal 14.31818MHz to meet Input Low Current Powerdown Current IDD3.3PD Input Capacitance 1 |
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