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TMS320DM6433ZDU6 Datasheet(PDF) 2 Page - Texas Instruments

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Part # TMS320DM6433ZDU6
Description  Digital Media Processor
Download  271 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

TMS320DM6433ZDU6 Datasheet(HTML) 2 Page - Texas Instruments

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1.2 Description
TMS320DM6433
Digital Media Processor
SPRS343C – NOVEMBER 2006 – REVISED JUNE 2008
www.ti.com
SPI
• Flexible PLL Clock Generators
Standard Voice Codec Interface (AIC12)
• IEEE-1149.1 (JTAG™)
Telecom Interfaces – ST-Bus, H-100
Boundary-Scan-Compatible
128 Channel Mode
• Up to 111 General-Purpose I/O (GPIO) Pins
• Multichannel Audio Serial Port (McASP0)
(Multiplexed With Other Device Functions)
Four Serializers and SPDIF (DIT) Mode
• Packages:
• 16-Bit Host-Port Interface (HPI)
361-Pin Pb-Free PBGA Package
(ZWT Suffix), 0.8-mm Ball Pitch
• 32-Bit 33-MHz, 3.3-V Peripheral Component
376-Pin Plastic BGA Package
Interconnect (PCI) Master/Slave Interface
(ZDU Suffix), 1.0-mm Ball Pitch
• 10/100 Mb/s Ethernet MAC (EMAC)
• 0.09-µm/6-Level Cu Metal Process (CMOS)
IEEE 802.3 Compliant
• 3.3-V and 1.8-V I/O, 1.2-V Internal
Supports Media Independent Interface (MII)
(-7/-6/-5/-4/-L/-Q6/-Q5/-Q4)
Management Data I/O (MDIO) Module
• 3.3-V and 1.8-V I/O, 1.05-V Internal
• VLYNQ™ Interface (FPGA Interface)
(-7/-6/-5/-4/-L/-Q5)
• Three Pulse Width Modulator (PWM) Outputs
• Applications:
• On-Chip ROM Bootloader
Digital Media
• Individual Power-Savings Modes
Networked Media Decode
The TMS320C64x+™ DSPs (including the TMS320DM6433 device) are the highest-performance
fixed-point DSP generation in the TMS320C6000™ DSP platform. The DM6433 device is based on the
third-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture
developed by Texas Instruments (TI), making these DSPs an excellent choice for digital media
applications. The C64x+™ devices are upward code-compatible from previous devices that are part of the
C6000™ DSP platform. The C64x™ DSPs support added functionality and have an expanded instruction
set from previous devices.
Any reference to the C64x DSP or C64x CPU also applies, unless otherwise noted, to the C64x+ DSP and
C64x+ CPU, respectively.
With performance of up to 5600 million instructions per second (MIPS) at a clock rate of 700 MHz, the
C64x+ core offers solutions to high-performance DSP programming challenges. The DSP core possesses
the operational flexibility of high-speed controllers and the numerical capability of array processors. The
C64x+ DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly
independent functional units—two multipliers for a 32-bit result and six arithmetic logic units (ALUs). The
eight functional units include instructions to accelerate the performance in video and imaging applications.
The DSP core can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 2800 million
MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 5600 MMACS. For more details
on the C64x+ DSP, see the TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide
(literature number SPRU732).
The DM6433 also has application-specific hardware logic, on-chip memory, and additional on-chip
peripherals similar to the other C6000 DSP platform devices. The DM6433 core uses a two-level
cache-based architecture. The Level 1 program memory/cache (L1P) consists of a 256K-bit memory
space that can be configured as mapped memory or direct mapped cache, and the Level 1 data (L1D)
consists of a 640K-bit memory space —384K-bit of which is mapped memory and 256K-bit of which can
be configured as mapped memory or 2-way set-associative cache. The Level 2 memory/cache (L2)
consists of a 1M-bit memory space that is shared between program and data space. L2 memory can be
configured as mapped memory, cache, or combinations of the two.
TMS320DM6433 Digital Media Processor
2
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