MDT10P432

This specification is subject to be changed without notice. Please visit our web site for the most updated information.

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10 of 13

2010.8

Ver. 1.5

TRIS

Data

Bus

Read

DFFPA

Latch

D

C

Q

PB

QB

Reset

PB1~7:

Pull_Hi 50K

Port

Output Pad

(B) PB1~7 Equivalent Circuit

14. Application circuit (reference)

(A). Enable internal 455KHz & 250 mA NMOS (Without BJT)

Note : Power Vdd & Vss must used metal line to IC Vdd & Vss with shortest distance

IR must used metal line to Vdd & PB0

VCC

VCC

S1

1

2

S2

1

2

S3

1

2

S4

1

2

S5

1

2

S6

1

2

S7

1

2

S8

1

2

S9

1

2

S10

1

2

S11

1

2

S12

1

2

S14

1

2

S15

1

2

S13

1

2

S16

1

2

S17

1

2

S18

1

2

S19

1

2

S20

1

2

S22

1

2

S23

1

2

S21

1

2

S24

1

2

S25

1

2

S28

1

2

S32

1

2

S30

1

2

S26

1

2

S31

1

2

S29

1

2

S27

1

2

S33

1

2

S34

1

2

S35

1

2

S36

1

2

S38

1

2

S39

1

2

S37

1

2

S40

1

2

S41

1

2

S44

1

2

S48

1

2

S46

1

2

S42

1

2

S47

1

2

S45

1

2

S43

1

2

S62

1

2

S64

1

2

S56

1

2

S55

1

2

S52

1

2

S50

1

2

S63

1

2

S60

1

2

S53

1

2

S51

1

2

S49

1

2

S59

1

2

S58

1

2

S57

1

2

S61

1

2

S54

1

2

U1

MDT10P432P21/S21

7

8

9

10

11

12

13

14

18

19

2

3

15

17

16

6

20

1

4

5

PB0

PB1

PB2

PB3

PB4

PB5

PB6

PB7

PA0

PA1

PA2

PA3

VDD

OSC1

OSC2

VSS

PA4

PA5

PA6

PA7

R1

10

10

D1

IR

C4

0.1u

+

C3

10u

C4 by-pass

capacitor must

closed the IC

Vdd and Vss