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MDT10P74P11 Datasheet(PDF) 6 Page - Micon Design Technology Corporation |
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MDT10P74P11 Datasheet(HTML) 6 Page - Micon Design Technology Corporation |
6 / 24 page MDT10P74(BB) This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 6 2010/10 Ver. 1.8 (5) MSR (Memory Bank Select Register): R04 Memory Bank Select Register 0: 00h~7Fh (Bank0) 1: 80h~FFh (Bank1) b7 b6 b5 b4 b3 b2 b1 b0 Indirect Addressing Mode (6) PORT A: R05 PA5~PA0, I/O Register (7) PORT B: R06 PB7~PB0, I/O Register (8) PORT C: R07 PC7~PC0, I/O Register (9) PORT D: R08 PD7~PD0, I/O Register (10) PORT E: R09 PE2~PE0, I/O Register (11) PCHLAT: R0A (12) INTS (Interrupt Status Register): R0B Bit Symbol Function 0 RBIF PORT B change interrupt flag, Set when PB <7:4> inputs change 1 INTF Set when INT interrupt occurs 2 TIF Set when TMR0 overflows 3 RBIE 0: Disable PB change interrupt 1: Enable PB change interrupt 4 INTS 0: Disable INT interrupt 1: Enable INT interrupt 5 TIS 0: Disable TMR0 interrupt 1: Enable TMR0 interrupt 6 PEIE 0: Disable all peripheral interrupt 1: Enable all peripheral interrupt 7 GIS 0: Disable global interrupt 1: Enable global interrupt |
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