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PLSI1032E-100LJ Datasheet(PDF) 10 Page - Lattice Semiconductor |
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PLSI1032E-100LJ Datasheet(HTML) 10 Page - Lattice Semiconductor |
10 / 17 page 10 Specifications ispLSI and pLSI 1032E Internal Timing Parameters1 tob 1. Internal Timing Parameters are not tested and are for reference only. Table 2-0037B/1032E Outputs UNITS -80 MIN. -70 MIN. MAX. MAX. DESCRIPTION # PARAM. 49 Output Buffer Delay – ns toen 51 I/O Cell OE to Output Enabled – ns tgy0 54 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock) 1.5 ns Global Reset Clocks tgr 59 Global Reset to GLB and I/O Registers – ns todis 52 I/O Cell OE to Output Disabled – ns tgy1/2 55 Clock Delay, Y1 or Y2 to Global GLB Clock Line 2.6 ns tgcp 56 Clock Delay, Clock GLB to Global GLB Clock Line 0.8 ns tioy2/3 57 Clock Delay, Y2 or Y3 to I/O Cell Global Clock Line 0.0 ns tiocp 58 Clock Delay, Clock GLB to I/O Cell Global Clock Line 0.8 ns tgoe 53 Global OE – ns MIN. MAX. tsl 50 Output Buffer Delay, Slew Limited Adder – ns 2.1 5.7 1.5 4.5 5.7 3.1 1.8 0.0 1.8 4.3 10.0 – – 1.5 – – 1.5 0.8 0.0 0.8 – – 2.6 6.2 1.5 4.6 6.2 1.5 1.8 0.0 1.8 5.8 10.0 -90 – – 1.4 – 2.4 0.8 0.0 0.8 – – – 1.7 5.3 1.4 4.5 5.3 2.9 1.8 0.0 1.8 3.7 10.0 |
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