10

Specifications ispLSI and pLSI 1032E

1. Internal Timing Parameters are not tested and are for reference only.

Table 2-0037B/1032E

Outputs

UNITS

-80

MIN.

-70

MIN.

MAX.

MAX.

DESCRIPTION

#

PARAM.

49 Output Buffer Delay

–

ns

51 I/O Cell OE to Output Enabled

–

ns

54 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock)

1.5

ns

Global Reset

Clocks

59 Global Reset to GLB and I/O Registers

–

ns

52 I/O Cell OE to Output Disabled

–

ns

55 Clock Delay, Y1 or Y2 to Global GLB Clock Line

2.6

ns

56 Clock Delay, Clock GLB to Global GLB Clock Line

0.8

ns

57 Clock Delay, Y2 or Y3 to I/O Cell Global Clock Line

0.0

ns

58 Clock Delay, Clock GLB to I/O Cell Global Clock Line

0.8

ns

53 Global OE

–

ns

MIN. MAX.

50 Output Buffer Delay, Slew Limited Adder

–

ns

2.1

5.7

1.5

4.5

5.7

3.1

1.8

0.0

1.8

4.3

10.0

–

–

1.5

–

–

1.5

0.8

0.0

0.8

–

–

2.6

6.2

1.5

4.6

6.2

1.5

1.8

0.0

1.8

5.8

10.0

-90

–

–

1.4

–

2.4

0.8

0.0

0.8

–

–

–

1.7

5.3

1.4

4.5

5.3

2.9

1.8

0.0

1.8

3.7

10.0