CLKIN

DOUT

Bitream not valid

(analog settling)

DVDD

...

Valid bitstream

AVDD

Test Pattern

CLKIN

DOUT

11

AMC1306E05, AMC1306E25, AMC1306M05, AMC1306M25

www.ti.com

SBAS734A – MARCH 2017 – REVISED JULY 2017

Product Folder Links: AMC1306E05 AMC1306E25 AMC1306M05 AMC1306M25

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Copyright © 2017, Texas Instruments Incorporated

(1)

The output of the Manchester encoded versions of the AMC1306Ex can change with every edge of CLKIN with a typical delay of 6 ns;

see the Manchester Coding Feature section for additional details.

7.11 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

CLKIN clock frequency

4.5 V

≤ AVDD ≤ 5.5 V

5

21

MHz

3.0 V

≤ AVDD ≤ 5.5 V

5

20

CLKIN clock period

4.5 V

≤ AVDD ≤ 5.5 V

47.6

200

ns

3.0 V

≤ AVDD ≤ 5.5 V

50

200

CLKIN clock high time

20

25

120

ns

CLKIN clock low time

20

25

120

ns

DOUT hold time after rising edge

of CLKIN

3.5

ns

Rising edge of CLKIN to DOUT

valid delay

15

ns

DOUT rise time

10% to 90%, 2.7 V

≤ DVDD ≤ 3.6 V,

0.8

3.5

ns

10% to 90%, 4.5 V

≤ DVDD ≤ 5.5 V,

1.8

3.9

DOUT fall time

90% to 10%, 2.7 V

≤ DVDD ≤ 3.6 V,

0.8

3.5

ns

90% to 10%, 4.5 V

≤ DVDD ≤ 5.5 V,

1.8

3.9

Interface startup time

DVDD at 2.7 V (min) to DOUT valid with

AVDD

≥ 3.0 V

32

32

CLKIN

cycles

Analog startup time

AVDD step to 3.0 V with DVDD

≥ 2.7 V,

0.1% settling

0.5

ms

Figure 1. Digital Interface Timing

Figure 2. Device Startup Timing