GS8673ET18/36BK-675/625/550/500

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Rev: 1.06 5/2012

10/34

© 2011, GSI Technology

DQ Input Termination Control

A robust methodology has been developed for these devices for controlling when DQ input termination is enabled and disabled

during Write-to-Read and Read-to-Write transitions. Specifically, the methodology can ensure that the DQ bus is never pulled to

could cause the receiver to enter a meta-stable state and consume more power than it normally would. This could result in the

device’s operating currents being higher.

The fundamental concept of the methodology is - both the ECCRAM and the Memory Controller drive the DQ bus Low (with DQ

input termination disabled) at all times except:

1. When a particular device is driving the DQ bus with valid data, and

2. From shortly before to shortly after a particular device is receiving valid data on the DQ bus, during which time the receiving

device enables its DQ termination.

And, during Write-to-Read and Read-to-Write transitions, each device enables and disables its DQ termination while the other

Note: This methodology also reduces power consumption, since there will be no DC current through either device’s DQs when

both devices are driving Low.

In order for this methodology to work as described, the Memory Controller must have the ability to:

1. Place the ECCRAM into “DQ Drive Low Mode” at the appropriate times (i.e. before and after the ECCRAM drives valid Read

Data), and

2. Place the ECCRAM into “DQ Termination Mode” at the appropriate times (i.e. before, during, and after the ECCRAM receives

valid Write Data).

That ability is provided via the existing R/W control pin.

When the ECCRAM samples R/W High (regardless of the state of LD), it disables its DQ termination, and drives the DQ bus Low

except while driving valid Read Data in response to Read operations.

When the ECCRAM samples R/W Low (regardless of the state of LD), it disables its DQ drivers, and enables its DQ termination.

Note that NOPs initiated with R/W High and LD High are referred to as “NOPr” operations.

Note that NOPs initiated with R/W Low and LD High are referred to as “NOPw” operations.

This extended definition of the R/W control pin allows the Memory Controller to:

•

Place the ECCRAM in DQ Termination Mode, via NOPw operations, before initiating Write operations.

•

Keep the ECCRAM in DQ Termination Mode, via NOPw operations, after initiating Write operations.

•

Place the ECCRAM in DQ Drive Low Mode, via NOPr operations, before initiating Read operations.

•

Keep the ECCRAM in DQ Drive Low Mode, via NOPr operations, after initiating Read operations.