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GS8673ED18BGK-625 Datasheet(PDF) 2 Page - GSI Technology |
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GS8673ED18BGK-625 Datasheet(HTML) 2 Page - GSI Technology |
2 / 32 page GS8673ED18/36BK-675/625/550/500 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Rev: 1.06 5/2012 2/31 © 2011, GSI Technology 4M x 18 (Top View) 1 2 3 4 5 6 7 8 9 10 11 12 13 A VDD VDDQ VDD VDDQ MCL MCH (CFG) MCL ZQ PZT1 VDDQ VDD VDDQ VDD B VSS NUO VSS NUI MVQ MCH (B4M) NC (RSVD) MCH (SIOM) PZT0 D0 VSS Q0 VSS C Q17 VDDQ D17 VDDQ VSS SA VDD SA VSS VDDQ NUI VDDQ NUO D VSS NUO VSS NUI SA VDDQ NC (288 Mb) VDDQ NC (144 Mb) D1 VSS Q1 VSS E Q16 VDDQ D16 VDD VSS SA VSS SA VSS VDD NUI VDDQ NUO F VSS NUO VSS NUI SA VDD VDDQ VDD SA D2 VSS Q2 VSS G Q15 NUO D15 NUI VSS SA MZT1 SA VSS D3 NUI Q3 NUO H Q14 VDDQ D14 VDDQ SA VDDQ W VDDQ SA VDDQ NUI VDDQ NUO J VSS NUO VSS NUI VSS SA VSS SA VSS D4 VSS Q4 VSS K CQ1 VDDQ VREF VDD KD1 VDD CK VDD KD0 VDD VREF VDDQ CQ0 L CQ1 VSS QVLD1 Vss KD1 VDDQ CK VDDQ KD0 VSS QVLD0 VSS CQ0 M VSS Q13 VSS D13 VSS SA VSS SA VSS NUI VSS NUO VSS N NUO VDDQ NUI VDDQ DLL VDDQ R VDDQ MCH VDDQ D5 VDDQ Q5 P NUO Q12 NUI D12 VSS SA MZT0 SA VSS NUI D6 NUO Q6 R VSS Q11 VSS D11 MCH VDD VDDQ VDD RST NUI VSS NUO VSS T NUO VDDQ NUI VDD VSS SA VSS SA VSS VDD D7 VDDQ Q7 U VSS Q10 VSS D10 NUI VDDQ ADZT1 VDDQ NUI NUI VSS NUO VSS V NUO VDDQ NUI VDDQ VSS SA (x18) VDD NUI (B2) VSS VDDQ D8 VDDQ Q8 W VSS Q9 VSS D9 TCK RLM0 NC (RSVD) MCL TMS NUI VSS NUO VSS Y VDD VDDQ VDD VDDQ TDO ZT RLM1 MCL TDI VDDQ VDD VDDQ VDD Notes: 1. Pins 5A and 7A are reserved for future use. They must be tied Low in this device. 2. Pins 5R and 9N are reserved for future use. They must be tied High in this device. 3. Pin 6A is defined as mode pin CFG in the pinout standard. It must be tied High in this device to select x18 configuration. 4. Pin 8B is defined as mode pin SIOM in the pinout standard. It must be tied High in this device to select Separate I/O configuration. 5. Pin 6B is defined as mode pin B4M in the pinout standard. It must be tied High in this device to select Burst-of-4 configuration. 6. Pin 6V is defined as address pin SA for x18 devices. It is used in this device. 7. Pin 8V is defined as address pin SA for B2 devices. It is unused in this device, and must be left unconnected or driven Low. 8. Pin 9D is reserved as address pin SA for 144 Mb devices. It is a true no connect in this device. 9. Pin 7D is reserved as address pin SA for 288 Mb devices. It is a true no connect in this device. 10. Pins 5U and 9U are unused in this device. They must be left unconnected or driven Low. 11. Pins 8W and 8Y are reserved for internal use only. They must be tied Low. 12. Pins 7B and 7W are reserved for future use. They are true no connects in this device. |
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