Electronic Components Datasheet Search |
|
GS8673ED18BGK-550 Datasheet(PDF) 7 Page - GSI Technology |
|
GS8673ED18BGK-550 Datasheet(HTML) 7 Page - GSI Technology |
7 / 32 page GS8673ED18/36BK-675/625/550/500 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Rev: 1.06 5/2012 7/31 © 2011, GSI Technology Reset (RST) Requirements Although not generally recommended, RST may be asserted High at any time after completion of the initial power-up sequence described previously, to reset the SRAM control logic to its initial power-on state. However, whenever RST is subsequently de-asserted Low (as in Step 4 in the power up sequence), Steps 5~7 in the power-up sequence must be followed before Read and Write operations are initiated. Note: Memory array content may be perturbed/corrupted when RST is asserted High. DLL Operation An on-chip DLL is used to align output timing with input clocks. The DLL uses the CK input clock as a source, and is enabled when all of the following conditions are met: 1. The DLL pin is asserted High, and 2. The RST pin is de-asserted Low, and 3. The input clock tKHKH ≤ 6.0ns. Once enabled, the DLL requires 64K (65,536) stable clock cycles in order to synchronize properly. The DLL can tolerate changes in input clock frequency due to clock jitter (i.e. such jitter will not cause the DLL to lose lock/ synchronization), provided the cycle-to-cycle jitter does not exceed 200ps (see the tKJITcc specification in the AC Electrical Characteristics section for more information). However, the DLL must be resynchronized (i.e. disabled and then re-enabled) whenever the nominal input clock frequency is changed. When the DLL is enabled, read latency is determined by the RLM mode pins, as defined in the Read Latency section. Output timing is aligned with the input clocks. The DLL is disabled when any of the following conditions are met: 1. The DLL pin is de-asserted Low, or 2. The RST pin is asserted High, or 3. The input clock is stopped for at least 30ns, or tKHKH ≥ 30ns. On-Chip Error Correction SigmaQuad-IIIe ECCRAMs implement a single-bit error detection and correction algorithm (specifically, a Hamming Code) on each DDR data word (comprising two 9-bit data bytes) transmitted on each 9-bit data bus (i.e., transmitted on D/Q[8:0], D/Q[17:9], D/Q[26:18], or D/Q[35:27]). To accomplish this, 5 ECC parity bits (invisible to the user) are utilized per every 18 data bits (visible to the user). The ECC algorithm neither corrects nor detects multi-bit errors. However, GSI ECCRAMs are architected in such a way that a single SER event very rarely causes a multi-bit error across any given “transmitted data unit”, where a “transmitted data unit” represents the data transmitted as the result of a single read or write operation to a particular address. The extreme rarity of multi-bit errors results in the SER mentioned previously (i.e., <0.002 FITs/Mb (measured at sea level)). Not only does the on-chip ECC significantly improve SER performance, but it also frees up the entire memory array for data storage. Very often SRAM applications allocate 1/9th of the memory array (i.e., one “error bit” per eight “data bits”, in any 9-bit “data byte”) for error detection (either simple parity error detection, or system-level ECC error detection and correction). Such error-bit allocation is unnecessary with ECCRAMs the entire memory array can be utilized for data storage, effectively providing 12.5% greater storage capacity compared to SRAMs of the same density not equipped with on-chip ECC. |
Similar Part No. - GS8673ED18BGK-550 |
|
Similar Description - GS8673ED18BGK-550 |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.NET |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |