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SP3223EUCA-L Datasheet(PDF) 10 Page - Exar Corporation |
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SP3223EUCA-L Datasheet(HTML) 10 Page - Exar Corporation |
10 / 21 page Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (50)668-707 • www.exar.com SP3223E/EB/EU_0_06272 0 Receivers The receivers convert ±5.0V EIA/TIA-232 levels to TTL or CMOS logic output levels. Receivers have an inverting output that can be disabled by using the EN pin. Receivers are active when the AUTO ON- LINE® circuitry is enabled or when in shut- down.Duringtheshutdown,thereceiverswill continue to be active. If there is no activity present at the receivers for a period longer than00µsorwhenSHUTDOWNisenabled, the device goes into a standby mode where the circuit draws µA. Driving EN to a logic HIGH forces the outputs of the receivers into high-impedance. The truth table logic of the SP3223 driver and receiver outputs can be found in Table 2. Since receiver input is usually from a trans- mission line where long cable lengths and system interference can degrade the signal, the inputs have a typical hysteresis margin of 300mV. This ensures that the receiver is virtually immune to noisy transmission lines. Should an input be left unconnected, an internal 5kΩ pull-down resistor to ground will commit the output of the receiver to a HIGH state. Table 3. SHUTDOWN and EN Truth Tables Note: In AUTO ON-LINE® Mode where ONLINE = GND and SHUTDOWN = V CC, the device will shut down if there is no activity present at the Receiver inputs. Figure 4. Loopback Test Circuit for RS-232 Driver Data Transmission Rates Charge Pump The charge pump uses a unique approach compared to older less–efficient designs. The charge pump still requires four external capacitors, but uses a four–phase voltage shifting technique to attain symmetrical 5.5V power supplies. The internal power supply consists of a regulated dual charge pump that provides output voltages of +/-5.5V regardless of input voltage (V CC) over the +3.0V to +5.5V range. This is important to maintain compliant RS- 232 levels regardless of power supply fluctuations. Figure 5. Loopback Test Circuit result at 250Kbps (All Drivers Fully Loaded) Device: SP3223 SHUTDOWN EN T XOUT R XOUT 0 0 High Z Active 0 High Z High Z 0 Active Active Active High Z |
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