M2006-12A Datasheet Rev 1.0

5 of 10

Revised 28Jul2004

Integr ated Circuit Systems , Inc. ● Ne tw o r ki ng & C o mmun ica t io ns ● ww w. icst.com ● tel (508 ) 85 2-54 00

M2006-12A

Integrated

Circuit

Systems, Inc.

Automatic Phase Compensation (APC) Pin

The M2006-12A also includes a phase build-out

function that can be selectively enabled by asserting the

function works in conjunction with the HS function.

When the APC pin is asserted, the phase build-out

function enables the PLL to absorb most of the phase

change of the input clock which reduces re-lock time

and the generation of wander. (Wander is created in this

case by the generation of extra output clock cycles.)

When the APC pin is asserted, the phase build-out

function is triggered by same >4 ns phase transient (at

the phase detector) that triggers the HS function. Once

triggered, a new VCSO clock edge is selected for the

phase comparator feedback input. (The clock edge

selected is the one closest in phase to the new input

clock phase.) The residual phase detector phase error

following reselection is approximately 3-to-4 ns. The

narrow bandwidth selected by HS minimizes VCSO

drifting and switch transients during the process.

It is recommended that the APC pin remain low when

the phase detector frequency is less than 4 MHz.

Otherwise, the M2006-12A may have difficulty locking

to reference upon power-up.

Outputs

The M2006-12A provides a total of two differential

FOUT0

can output the two different frequencies at the

Any unused output should be left unconnected

(floating) in the system application. This will

minimize output switching current and therefore

minimize noise modulation of the VCSO.

External Loop Filter

To provide stable PLL operation, and thereby a low jitter

output clock, the M2006-12A requires the use of an

external loop filter. This is provided via the provided

filter pins (see Figure 4).

Due to the differential signal path design, the

implementation requires two identical complementary

RC filters as shown here.

Figure 4: External Loop Filter

See Example External Loop Filter Component Values table.

PLL bandwidth is affected by loop filter component

values, “Mfec” and “Mfin” values, and the “PLL Loop

Constants” listed in AC Characteristics on pg. 8.

The various “Non-FEC ratio” settings can be used to

actively change PLL loop bandwidth in a given

application. See “FEC PLL Ratio Dividers Look-up

Table (LUT)” on pg. 3.

PLL Simulator Tool Available

A free PC software utility is available on the ICS website

(www.icst.com). The M2000 Timing Modules PLL

Simulator is a downloadable application that simulates

PLL jitter and wander transfer characteristics. This

enables the user to set appropriate external loop

component values in a given application.

Go to the SAW PLL Simulator Software web page at

www.icst.com/products/calculators/m2000filterSWdesc.htm

C

POST

C

POST

VC

nVC

R

POST

nOP_OUT

OP_OUT

R

POST

R

LOOP

R

LOOP

C

LOOP

C

LOOP

OP_IN

nOP_IN

6

7

5

49

8

Device Configuration

Example External Loop Filter Component Values

Nominal Performance Using These Values

(MHz)

F

pins

FEC_ SEL3:0

pins

R loop

C loop

R post

C post

PLL Loop

Bandwidth

Damping

Factor

Passband

19.44

622.08

0 0

1 1 0 0

11.5

k

Ω

2.2

µF

34

k

Ω

470

pF

1k

Hz

6.0

0.05

77.76

0 1

1 1 1 0

155.52

1 0

1 1 1 1

622.08

1 1

0 1 1 0

5.11

k

Ω

4.7

µF

6.0

0.06

167.3317

1 0

0 0 0 1

113.0

k

Ω

0.22

µF

6.0

0.06

669.3266

1 1

28.0

k

Ω

1.0

µF

6.3

0.05

155.52

669.3266

1 0

1 0 0 1

121.0

k

Ω

0.22

µF

6.0

0.05

622.08

1 1

30.1

k

Ω

1.0

µF

6.5

0.05

Table 8: Example External Loop Filter Component Values

Note 1: K

Passband Peaking. For PLL Simulator software, go to www.icst.com.