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FC3255 Datasheet(PDF) 9 Page - First Components International |
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FC3255 Datasheet(HTML) 9 Page - First Components International |
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9 / 18 page  When the power switch turns off, there exists a volt- age spike superimposed on top of the steady-state voltage. Usually, this voltage spike is caused by transformer leakage inductance charging stray ca- pacitance between the V and PGND pins. To pres- SW ent the voltage at the V pin from exceeding the SW maximum rating, a transient voltage suppressor in series with a diode is paralleled with the primary windings. Another method of clamping switch volt- age is to connect a transient voltage suppressor be- tween the V pin and ground. SW Magnetic Component Selection When choosing a magnetic component, one must consider factors such as peak current, core and fer- rite material, output voltage ripple, EMI, temperature range, physical size, and cost. In boost circuits, the average inductor current is the product of output cur- rent and voltage gain (V / V ), assuming 100% OUT CC energy transfer efficiency. In continuous conduction mode, inductor ripple current is where: f = 280kHz. The peak inductor current is equal to average cur- rent plus half of the ripple current, which should not cause inductor saturation. The above equation can also be referenced when selecting the value of the inductor based on the tolerance of the ripple current in the circuits. Small ripple current provides the bene- fits of small input capacitors and greater output cur- rent capability. A core geometry like a rod or barrel is prone to generating high magnetic field radiation, but is relatively cheap and small. Other core geome- tries, such as toroids, provide a closed magnetic loop to prevent EMI. Input Capacitor Selection In boost circuits, the inductor becomes part of the input filter, as shown in Figure 11. In continuous mode, the input current waveform is triangular and does not contain a large pulsed current, During con- tinuous conduction mode, the peak to peak inductor ripple current is given in the previous section. In most applications, input capacitors in the range of 10µF to 100µF with an ESR less than 0.3W work well up to a full 1.5A switch current. The phase lead provided by this zero ensures that the loop has at least a 45°C phase margin at the cross- over frequency. Therefore, this zero should be placed close to the pole generated in the power stage, which can be identified at frequency: where: The high frequency pole, f , can be placed at the out- P2 put filter's ESR zero or at half the switching frequency. Placing the pole at this frequency will cut down on switching noise. The frequency of this pole is deter- mined by the value of C2 and R1: One simple method to ensure adequate phase margin is to design the frequency response with a - 20 dB per decade slope, until unity-gain crossover. The crossover frequency should be selected at the midpoint between f and f where the phase margin is maximized. Z1 P2 V Voltage Limit SW In the boost topology, V pin maximum voltage is set SW by the maximum output voltage plus the output diode forward voltage. The diode forward voltage is typically 0.5V for Schottky diodes and 0.8V for ultrafast diodes Where: Where: N = transformer turns ratio, primary over secondary C = equivalent output capacitance of the error O amplifier 120pF; R = load resistance. LOAD f = P1 1 2pCR O LOAD V = V + V SW(MAX) OUT(MAX) F V = output diode forward voltage. F In the flyback topology, peak V voltage is governed by: SW V = V + (V + V ) X N SW(MAX) CC(MAX) OUT F f = P2 1 2pC1R1 Frequency(LOG) f P1 F P2 f Z1 Figure 10. Bode Plot of the Compensation Network Shown in Figure 9. I = RIPPLE V (V - V ) CC OUT CC ( f )( L )(V ) OUT FC3255 1.5A PWM Switching Regulators |
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