SDA line operates as both an input and an open-drain

output. A pullup resistor, typically 4.7kΩ, is required on

SDA. The SCL line operates only as an input. A pullup

resistor, typically 4.7kΩ, is required on SCL if there are

multiple masters on the 2-wire bus, or if the master in a

single-master system has an open-drain SCL output.

Start and Stop Conditions

Both SCL and SDA remain high when the interface is

idle. The active master signals the beginning of a trans-

mission with a START (S) condition by transitioning

SDA from high to low while SCL is high. After communi-

cation, the MAX9485 issues a STOP (P) condition by

transitioning SDA from low to high while SCL is high,

freeing the bus for another transmission (Figure 5). If a

START or STOP occurs while a bus transaction is in

progress, then it terminates the transaction.

Data Transfer and Acknowledge

Following the START condition, each SCL clock pulse

transfers 1 bit. For the MAX9485 interface, between a

START and a STOP, 18 bits are transferred on the

2-wire bus. The first 7 bits are for the device address.

Bit 8 indicates the writing (low) or reading (high) opera-

tion (R/W). Bit 9 is the ACK for the address and opera-

tion type. Bits 10 though 17 form the data byte. Bit 18 is

the ACK for the data byte. The master always transfers

the first 8 bits (address + R/W). The slave (MAX9485)

can receive the data byte from the bus or transfer it to

the bus from the internal register. The ACK bits are

transmitted by the address or data recipient. A low

ACK bit indicates a successful transfer (Acknowledge),

a high ACK bit indicates an unsuccessful transfer (Not

Acknowledge). Figure 6 shows the structure of the data

transfer. During a write operation, if more synchronous

data is transferred, it overwrites the data in the register.

During a read operation, if more clocks are reset on

SCL, the SDA continues to respond to the register data.

Programmable Audio Clock Generator

______________________________________________________________________________________

11

C3

C2

OUTPUT SCALING FACTOR

00

256

01

384

10

768

11

Reserved

Table 13. Frequency Scaling Factors

C1

C0

SAMPLING FREQUENCY (kHz)

00

12

01

32

10

44.1

11

48

SDA

SCL

START

CONDITION

STOP

CONDITION

S

P

Table 14. Sampling Frequency Selection

Note: (C1, C0) = (0, 0) and C4 = 1 (double) is not a proper selec-

tion. However, when set, it selects 12kHz sampling frequency.

Figure 5. Start and Stop Conditions

S

SLAVE ADDRESS

7 BITS

R/W

A

A = ACK; A = 0: ACKNOWLEDGE, A = 1: NOT ACKNOWLEDGE

S = START CONDITION

P = STOP CONDITION

MASTER-WRITE DATA STRUCTURE

MASTER TRANSFERS TO SLAVE

SLAVE TRANSFERS TO MASTER

MASTER-READ DATA STRUCTURE

DATA

8 BITS

P

A

A

R/W

SLAVE ADDRESS

7 BITS

S

DATA

8 BITS

P

A

Figure 6. Serial Interface Data Structure