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MC56F8322 Datasheet(PDF) 4 Page - Motorola, Inc |
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MC56F8322 Datasheet(HTML) 4 Page - Motorola, Inc |
4 / 136 page 56F8322 Techncial Data, Rev. 10.0 4 Freescale Semiconductor Preliminary Part 1: Overview . . . . . . . . . . . . . . . . . . . . . . 5 1.1. 56F8322/56F8122 Features . . . . . . . . . . . . . 5 1.2. Device Description . . . . . . . . . . . . . . . . . . . . 7 1.3. Award-Winning Development Environment . 8 1.4. Architecture Block Diagram . . . . . . . . . . . . . 9 1.5. Product Documentation . . . . . . . . . . . . . . . 13 1.6. Data Sheet Conventions . . . . . . . . . . . . . . . 13 Part 2: Signal/Connection Descriptions . . 14 2.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.2. Signal Pins . . . . . . . . . . . . . . . . . . . . . . . . . 17 Part 3: On-Chip Clock Synthesis (OCCS) . 26 3.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.2. External Clock Operation . . . . . . . . . . . . . . 26 3.3. Use of On-Chip Relaxation Oscillator . . . . . 28 3.4. Internal Clock Operation . . . . . . . . . . . . . . . 28 3.5. Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Part 4: Memory Map . . . . . . . . . . . . . . . . . . 30 4.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.2. Program Map . . . . . . . . . . . . . . . . . . . . . . . 30 4.3. Interrupt Vector Table . . . . . . . . . . . . . . . . . 31 4.4. Data Map . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4.5. Flash Memory Map . . . . . . . . . . . . . . . . . . . 34 4.6. EOnCE Memory Map . . . . . . . . . . . . . . . . . 36 4.7. Peripheral Memory Mapped Registers . . . . 36 4.8. Factory-Programmed Memory . . . . . . . . . . 52 Part 5: Interrupt Controller (ITCN) . . . . . . . 52 5.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 52 5.2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 5.3. Functional Description . . . . . . . . . . . . . . . . 52 5.4. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . 54 5.5. Operating Modes . . . . . . . . . . . . . . . . . . . . 54 5.6. Register Descriptions . . . . . . . . . . . . . . . . . 55 5.7. Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Part 6: System Integration Module (SIM) . . 77 6.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 77 6.2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 6.3. Operating Modes . . . . . . . . . . . . . . . . . . . . 78 6.4. Operating Mode Register . . . . . . . . . . . . . . 79 6.5. Register Descriptions . . . . . . . . . . . . . . . . . 79 6.6. Clock Generation Overview . . . . . . . . . . . . 91 6.7. Power-Down Modes . . . . . . . . . . . . . . . . . . 91 6.8. Stop and Wait Mode Disable Function . . . . 92 6.9. Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Part 7: Security Features . . . . . . . . . . . . . . 93 7.1. Operation with Security Enabled . . . . . . . . . 93 7.2. Flash Access Blocking Mechanisms . . . . . . 93 Part 8: General Purpose Input/Output (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . 96 8.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . .96 8.2. Configuration . . . . . . . . . . . . . . . . . . . . . . . .96 8.3. Memory Maps . . . . . . . . . . . . . . . . . . . . . . . .98 Part 9: Joint Test Action Group (JTAG) . . . 98 9.1. JTAG Information . . . . . . . . . . . . . . . . . . . . .98 Part 10: Specifications . . . . . . . . . . . . . . . . 99 10.1. General Characteristics . . . . . . . . . . . . . . .99 10.2. DC Electrical Characteristics . . . . . . . . . .103 10.3. AC Electrical Characteristics . . . . . . . . . .107 10.4. Flash Memory Characteristics . . . . . . . . .108 10.5. External Clock Operation Timing . . . . . . .109 10.6. Phase Locked Loop Timing . . . . . . . . . . .110 10.7. Oscillator Parameters . . . . . . . . . . . . . . . .110 10.8. Reset, Stop, Wait, Mode Select, and Interrupt Timing . . . . . . . . . . . . . .113 10.9. Serial Peripheral Interface (SPI) Timing . .115 10.10. Quad Timer Timing . . . . . . . . . . . . . . . . .118 10.11. Quadrature Decoder Timing . . . . . . . . . .118 10.12. Serial Communication Interface (SCI) Timing . . . . . . . . . . . . . . . . . . . . .119 10.13. Controller Area Network (CAN) Timing .120 10.14. JTAG Timing . . . . . . . . . . . . . . . . . . . . . .120 10.15. Analog-to-Digital Converter (ADC) Parameters . . . . . . . . . . . . . . . . .122 10.16. Equivalent Circuit for ADC Inputs . . . . . .125 10.17. Power Consumption . . . . . . . . . . . . . . . .125 Part 11: Packaging . . . . . . . . . . . . . . . . . . 127 11.1. 56F8322 Package and Pin-Out Information . . . . . . . . . . . . . . . . . .127 11.2. 56F8122 Package and Pin-Out Information . . . . . . . . . . . . . . . . . .129 Part 12: Design Considerations . . . . . . . . 132 12.1. Thermal Design Considerations . . . . . . . .132 12.2. Electrical Design Considerations . . . . . . .133 12.3. Power Distribution and I/O Ring Implementation . . . . . . . . . . . . . .134 Part 13: Ordering Information . . . . . . . . . 135 Table of Contents |
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