M5M5J167KT - 70HI

Jan.10,2003 Ver. 2.1

16777216-BIT (1048576-WORD BY 16-BIT / 2097152-WORD BY 8-BIT) CMOS STATIC RAM

MITSUBISHI LSIs

7

Note 5: Hatching indicates the state is "don't care".

Note 6: A Write occurs during S1# low, S2 high ov erlaps BC1# and/or BC2# low and W# low.

Note 8: Don't apply inv erted phase signal externally when DQ pin is in output mode.

Note 7: When the f alling edge of W# is simultaneously or prior to the f alling edge of BC1# and/or BC2# or the f alling edge of

S1# or rising edge of S2, the outputs are maintained in the high impedance state.

W#

Write cycle (BC# control mode)

(Note5)

(Note5)

(Note6)

(Note7)

(Note5)

(Note5)

S1#

BC1#,

BC2#

(Note5)

(Note5)

S2

S2

(Note5)

(Note5)

OE#

W#

Write cycle( W# control mode )

(Note5)

(Note5)

S1#

(Note5)

(Note5)

BC1#,

BC2#

DATA IN

STABLE

DATA IN

STABLE

(Word Mode)

(Byte Mode)

(Word Mode)

(Byte Mode)

(Word Mode)

(Byte Mode)

(Word Mode)

(Byte Mode)