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NS486SXL Datasheet(PDF) 4 Page - National Semiconductor (TI) |
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NS486SXL Datasheet(HTML) 4 Page - National Semiconductor (TI) |
4 / 6 page 1.0 System Overview (Continued) Certain I/O lines not being used by disabled peripherals can be reconfigured for use as general purpose bidirectional I/O lines (up to 28 pins). This gives the designer maximum flex- ibility in designing various systems using the NS486SXL de- vice. It is expected that an NS486SXL system will minimally include the NS486SXL system controller with on-board pro- cessor and I/O devices, boot ROM, and working RAM memory. Many applications will not require any additional I/O support. Finally, the NS486SXL implements a very flexible power management scheme that permits selective control of indi- vidual I/O subsystems, with varying levels of power con- sumption. NS486SXL provides a cost-effective hardware platform for the design and implementation of a wide range of internet appliance, networking and communication systems. With its powerful embedded ’486-class processor, comprehensive set of on-chip peripheral controllers, flexible power manage- ment structure and reconfigurable I/O lines, NS486SXL makes possible a variety of end-user systems based on the same hardware. Because of its optimized design and on- board resources, a very cost effective system can be achieved. 1.2 32-BIT PROCESSOR CORE The NS486SXL processor core is an implementation of the protected mode ’486 instruction set architecture, optimized using a RISC-like design philosophy for embedded applica- tions. Using this approach, the most frequently used instruc- tions are optimized, and on an average execute in a lower number of clock cycles than a ’486. The NS486SXL features a three stage pipeline, efficient in- struction prefetching mechanism, and single cycle instruc- tion decoding for most instructions. Additionally, a 1 Kbyte in- struction cache and single cycle DRAM access provide higher memory performance than a larger unified cache implementation. The NS486SXL processor provides the same programming model and register set as the standard ’486 except that real mode, virtual memory, and floating point support have been eliminated. These features have little or no impact in embed- ded applications and save significant silicon real estate. At reset, unlike the standard ’486, the NS486SXL starts up in protected mode instead of real mode. All ’486 instructions appropriate to protected mode and our hardware configura- tion are supported, including debug instructions. The NS486SXL is initially available to run 25 MHz at 5V. The processor clock is obtained by dividing the crystal frequency by two. For example, a 25 MHz NS486SXL runs with a 50 MHz crystal oscillator as the master clock. As a result of our innovative design, the NS486SXL achieves performance equivalent to a standard ’486 with less circuitry. This translates into reduced power consumption and a lower overall system cost. It also makes the NS486SXL ideal for “green” systems and battery operated systems. 1.3 SYSTEM SERVICE ELEMENTS The NS486SXL controller provides the basic hardware re- sources required for the O/S-defined System Service Ele- ments. These include a DRAM controller, programmable in- terval timer, a protected WATCHDOG timer, a programmable interrupt controller, a real-time clock and calendar, and com- prehensive power management features. 1.3.1 DRAM Controller The NS486SXL DRAM controller supports one or two adjustable-sized banks of dynamic RAM using a 16-bit data path. Support is provided for byte parity (if desired), requiring the DRAM banks to be 18-bits wide when parity is enabled. Banks can be up to 8 Mbytes in size. The DRAM controller supports page mode read and write operations and can also support both byte and word accesses. All access control sig- nals for read, write and parity checking are generated as well as an automatic and programmable CAS-before-RAS re- fresh. If self-refresh DRAMs are used, refresh can be dis- abled, saving power. NS486SXL provides flexible support for use of a number of different DRAM configurations, using popular DRAM de- vices. Access is optimized for fast page mode DRAMs, and they will provide the highest performance with contiguous data. When accessing data bytes or words in the same DRAM page, the data access is in one cycle. This perfor- mance provides fast data access times without the overhead of a separate data cache. Page sizes can be 512, 1024, 2048 or 4096 bytes. Flexibility for DRAM timing is provided through programming of the DRAM controller registers: 3 or 4 cycle page miss accesses and extended CAS cycles can be selected. Memory bank 0 starts at address 0h; memory bank 1 can start at any address in the 128 Mbyte address map that is a multiple of its size. 1.3.2 Programmable Interval Timer The NS486SXL programmable interval timer is compatible with the Intel 8254 programmable interval timer and contains three identical timers (CH0–CH2). CH0 and CH1 can be used to generate accurate timing delays under software con- trol. CH2 may be configured to provide a WATCHDOG timer function. 1.3.3 WATCHDOG Timer The NS486SXL WATCHDOG timer, CH2, is a protected 16- bit timer that can be used to prevent system “lockups or hangups.” It uses a 1 kHz clock generated by the on-chip real-time clock circuit. If the WATCHDOG timer is enabled and times out, a reset or interrupt will be generated allowing graceful recovery from an unexpected system lockup. 1.3.4 Interrupt Controller The NS486SXL interrupt controller consists of two cascaded programmable interrupt controllers that are compatible with the Intel 8259A Programmable Interrupt Controller. They pro- vide a total of 15 (out of 16) programmable interrupts. Three interrupts are reserved for a real time clock-tick interrupt, a real time clock interrupt request, and a cascade interrupt channel. The remaining 13 interrupts can be used by internal or external sources. Additional external interrupt controllers can be cascaded as well. 1.3.5 Real Time Clock/Calendar The NS486SXL Real Time Clock/Calendar is a low power clock that provides a time-of-day clock and 100-year calen- dar with alarm features and battery operation. Time is kept in BCD or binary format. It includes 50 bytes of general pur- pose CMOS RAM and 3 maskable interrupt sources. It is compatible with the DS1287 and MC146818 RTC/Calendar devices, except for the general purpose memory size. www.national.com 4 |
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